1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
4  */
5 
6 #ifndef __TPS65910_PMIC_H_
7 #define __TPS65910_PMIC_H_
8 
9 #define TPS65910_I2C_SEL_MASK		(0x1 << 4)
10 #define TPS65910_VDD_SR_MASK		(0x1 << 7)
11 #define TPS65910_GAIN_SEL_MASK		(0x3 << 6)
12 #define TPS65910_VDD_SEL_MASK		0x7f
13 #define TPS65910_VDD_SEL_MIN		3
14 #define TPS65910_VDD_SEL_MAX		75
15 #define TPS65910_SEL_MASK		(0x3 << 2)
16 #define TPS65910_SUPPLY_STATE_MASK	0x3
17 #define TPS65910_SUPPLY_STATE_OFF	0x0
18 #define TPS65910_SUPPLY_STATE_ON	0x1
19 
20 /* TPS65910 DEVICE_CTRL bits */
21 #define   PWR_OFF_SEQ			BIT(7)
22 #define   DEV_OFF_RST			BIT(3)
23 #define   DEV_ON			BIT(2)
24 #define   DEV_OFF			BIT(0)
25 
26 /* i2c registers */
27 enum {
28 	TPS65910_REG_RTC_SEC			= 0x00,
29 	TPS65910_REG_RTC_MIN,
30 	TPS65910_REG_RTC_HOUR,
31 	TPS65910_REG_RTC_DAY,
32 	TPS65910_REG_RTC_MONTH,
33 	TPS65910_REG_RTC_YEAR,
34 	TPS65910_REG_RTC_WEEK,
35 	TPS65910_REG_RTC_ALARM_SEC		= 0x08,
36 	TPS65910_REG_RTC_ALARM_MIN,
37 	TPS65910_REG_RTC_ALARM_HOUR,
38 	TPS65910_REG_RTC_ALARM_DAY,
39 	TPS65910_REG_RTC_ALARM_MONTH,
40 	TPS65910_REG_RTC_ALARM_YEAR,
41 	TPS65910_REG_RTC_CTRL			= 0x10,
42 	TPS65910_REG_RTC_STAT,
43 	TPS65910_REG_RTC_INT,
44 	TPS65910_REG_RTC_COMP_LSB,
45 	TPS65910_REG_RTC_COMP_MSB,
46 	TPS65910_REG_RTC_RESISTOR_PRG,
47 	TPS65910_REG_RTC_RESET_STAT,
48 	TPS65910_REG_BACKUP1,
49 	TPS65910_REG_BACKUP2,
50 	TPS65910_REG_BACKUP3,
51 	TPS65910_REG_BACKUP4,
52 	TPS65910_REG_BACKUP5,
53 	TPS65910_REG_PUADEN,
54 	TPS65910_REG_REF,
55 	TPS65910_REG_VRTC,
56 	TPS65910_REG_VIO			= 0x20,
57 	TPS65910_REG_VDD1,
58 	TPS65910_REG_VDD1_VAL,
59 	TPS65910_REG_VDD1_VAL_SR,
60 	TPS65910_REG_VDD2,
61 	TPS65910_REG_VDD2_VAL,
62 	TPS65910_REG_VDD2_VAL_SR,
63 	TPS65910_REG_VDD3,
64 	TPS65910_REG_VDIG1			= 0x30,
65 	TPS65910_REG_VDIG2,
66 	TPS65910_REG_VAUX1,
67 	TPS65910_REG_VAUX2,
68 	TPS65910_REG_VAUX33,
69 	TPS65910_REG_VMMC,
70 	TPS65910_REG_VPLL,
71 	TPS65910_REG_VDAC,
72 	TPS65910_REG_THERM,
73 	TPS65910_REG_BATTERY_BACKUP_CHARGE,
74 	TPS65910_REG_DCDC_CTRL			= 0x3e,
75 	TPS65910_REG_DEVICE_CTRL,
76 	TPS65910_REG_DEVICE_CTRL2,
77 	TPS65910_REG_SLEEP_KEEP_LDO_ON,
78 	TPS65910_REG_SLEEP_KEEP_RES_ON,
79 	TPS65910_REG_SLEEP_SET_LDO_OFF,
80 	TPS65910_REG_SLEEP_SET_RES_OFF,
81 	TPS65910_REG_EN1_LDO_ASS,
82 	TPS65910_REG_EM1_SMPS_ASS,
83 	TPS65910_REG_EN2_LDO_ASS,
84 	TPS65910_REG_EM2_SMPS_ASS,
85 	TPS65910_REG_INT_STAT			= 0x50,
86 	TPS65910_REG_INT_MASK,
87 	TPS65910_REG_INT_STAT2,
88 	TPS65910_REG_INT_MASK2,
89 	TPS65910_REG_GPIO			= 0x60,
90 	TPS65910_REG_JTAGREVNUM			= 0x80,
91 	TPS65910_NUM_REGS
92 };
93 
94 /* chip supplies */
95 enum {
96 	TPS65910_SUPPLY_VCCIO	= 0x00,
97 	TPS65910_SUPPLY_VCC1,
98 	TPS65910_SUPPLY_VCC2,
99 	TPS65910_SUPPLY_VCC3,
100 	TPS65910_SUPPLY_VCC4,
101 	TPS65910_SUPPLY_VCC5,
102 	TPS65910_SUPPLY_VCC6,
103 	TPS65910_SUPPLY_VCC7,
104 	TPS65910_NUM_SUPPLIES
105 };
106 
107 /* regulator unit numbers */
108 enum {
109 	TPS65910_UNIT_VRTC = 0x00,
110 	TPS65910_UNIT_VIO,
111 	TPS65910_UNIT_VDD1,
112 	TPS65910_UNIT_VDD2,
113 	TPS65910_UNIT_VDD3,
114 	TPS65910_UNIT_VDIG1,
115 	TPS65910_UNIT_VDIG2,
116 	TPS65910_UNIT_VPLL,
117 	TPS65910_UNIT_VDAC,
118 	TPS65910_UNIT_VAUX1,
119 	TPS65910_UNIT_VAUX2,
120 	TPS65910_UNIT_VAUX33,
121 	TPS65910_UNIT_VMMC,
122 };
123 
124 /* platform data */
125 struct tps65910_regulator_pdata {
126 	u32 supply;	/* regulator supply voltage in uV */
127 	uint unit;	/* unit-address according to DT */
128 };
129 
130 /* driver names */
131 #define TPS65910_BUCK_DRIVER	"tps65910_buck"
132 #define TPS65910_BOOST_DRIVER	"tps65910_boost"
133 #define TPS65910_LDO_DRIVER	"tps65910_ldo"
134 #define TPS65910_RST_DRIVER	"tps65910_rst"
135 
136 /* tps65911 i2c registers */
137 enum {
138 	TPS65911_REG_VIO			= 0x20,
139 	TPS65911_REG_VDD1,
140 	TPS65911_REG_VDD1_OP,
141 	TPS65911_REG_VDD1_SR,
142 	TPS65911_REG_VDD2,
143 	TPS65911_REG_VDD2_OP,
144 	TPS65911_REG_VDD2_SR,
145 	TPS65911_REG_VDDCTRL,
146 	TPS65911_REG_VDDCTRL_OP,
147 	TPS65911_REG_VDDCTRL_SR,
148 	TPS65911_REG_LDO1			= 0x30,
149 	TPS65911_REG_LDO2,
150 	TPS65911_REG_LDO5,
151 	TPS65911_REG_LDO8,
152 	TPS65911_REG_LDO7,
153 	TPS65911_REG_LDO6,
154 	TPS65911_REG_LDO4,
155 	TPS65911_REG_LDO3,
156 };
157 
158 #define TPS65911_VDD_NUM		4
159 #define TPS65911_LDO_NUM		8
160 
161 #define TPS65911_VDD_VOLT_MAX		1500000
162 #define TPS65911_VDD_VOLT_MIN		600000
163 #define TPS65911_VDD_VOLT_BASE		562500
164 
165 #define TPS65911_LDO_VOLT_MAX		3300000
166 #define TPS65911_LDO_VOLT_BASE		800000
167 
168 #define TPS65911_LDO_SEL_MASK		(0x3f << 2)
169 
170 #define TPS65911_LDO124_VOLT_MAX_HEX	0x32
171 #define TPS65911_LDO358_VOLT_MAX_HEX	0x19
172 #define TPS65911_LDO358_VOLT_MIN_HEX	0x02
173 
174 #define TPS65911_LDO124_VOLT_STEP	50000
175 #define TPS65911_LDO358_VOLT_STEP	100000
176 
177 #define TPS65911_VDD_DRIVER		"tps65911_vdd"
178 #define TPS65911_LDO_DRIVER		"tps65911_ldo"
179 
180 #endif /* __TPS65910_PMIC_H_ */
181