1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _QCOM_GENI_SE 7 #define _QCOM_GENI_SE 8 9 /* Protocols supported by GENI Serial Engines */ 10 enum geni_se_protocol_type { 11 GENI_SE_NONE, 12 GENI_SE_SPI, 13 GENI_SE_UART, 14 GENI_SE_I2C, 15 GENI_SE_I3C, 16 GENI_SE_SPI_SLAVE, 17 }; 18 19 #define QUP_HW_VER_REG 0x4 20 21 /* Common SE registers */ 22 #define GENI_INIT_CFG_REVISION 0x0 23 #define GENI_S_INIT_CFG_REVISION 0x4 24 #define GENI_FORCE_DEFAULT_REG 0x20 25 #define GENI_OUTPUT_CTRL 0x24 26 #define GENI_CGC_CTRL 0x28 27 #define SE_GENI_STATUS 0x40 28 #define GENI_SER_M_CLK_CFG 0x48 29 #define GENI_SER_S_CLK_CFG 0x4c 30 #define GENI_IF_DISABLE_RO 0x64 31 #define GENI_FW_REVISION_RO 0x68 32 #define SE_GENI_CLK_SEL 0x7c 33 #define SE_GENI_CFG_SEQ_START 0x84 34 #define SE_GENI_BYTE_GRAN 0x254 35 #define SE_GENI_DMA_MODE_EN 0x258 36 #define SE_GENI_TX_PACKING_CFG0 0x260 37 #define SE_GENI_TX_PACKING_CFG1 0x264 38 #define SE_GENI_RX_PACKING_CFG0 0x284 39 #define SE_GENI_RX_PACKING_CFG1 0x288 40 #define SE_GENI_M_CMD0 0x600 41 #define SE_GENI_M_CMD_CTRL_REG 0x604 42 #define SE_GENI_M_IRQ_STATUS 0x610 43 #define SE_GENI_M_IRQ_EN 0x614 44 #define SE_GENI_M_IRQ_CLEAR 0x618 45 #define SE_GENI_S_CMD0 0x630 46 #define SE_GENI_S_CMD_CTRL_REG 0x634 47 #define SE_GENI_S_IRQ_STATUS 0x640 48 #define SE_GENI_S_IRQ_EN 0x644 49 #define SE_GENI_S_IRQ_CLEAR 0x648 50 #define SE_GENI_TX_FIFOn 0x700 51 #define SE_GENI_RX_FIFOn 0x780 52 #define SE_GENI_TX_FIFO_STATUS 0x800 53 #define SE_GENI_RX_FIFO_STATUS 0x804 54 #define SE_GENI_TX_WATERMARK_REG 0x80c 55 #define SE_GENI_RX_WATERMARK_REG 0x810 56 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814 57 #define SE_GENI_IOS 0x908 58 #define SE_DMA_TX_IRQ_STAT 0xc40 59 #define SE_DMA_TX_IRQ_CLR 0xc44 60 #define SE_DMA_TX_FSM_RST 0xc58 61 #define SE_DMA_RX_IRQ_STAT 0xd40 62 #define SE_DMA_RX_IRQ_CLR 0xd44 63 #define SE_DMA_RX_LEN_IN 0xd54 64 #define SE_DMA_RX_FSM_RST 0xd58 65 #define SE_GSI_EVENT_EN 0xe18 66 #define SE_IRQ_EN 0xe1c 67 #define SE_HW_PARAM_0 0xe24 68 #define SE_HW_PARAM_1 0xe28 69 70 /* GENI_FORCE_DEFAULT_REG fields */ 71 #define FORCE_DEFAULT BIT(0) 72 73 /* GENI_OUTPUT_CTRL fields */ 74 #define GENI_IO_MUX_0_EN BIT(0) 75 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) 76 77 /* GENI_CGC_CTRL fields */ 78 #define CFG_AHB_CLK_CGC_ON BIT(0) 79 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1) 80 #define DATA_AHB_CLK_CGC_ON BIT(2) 81 #define SCLK_CGC_ON BIT(3) 82 #define TX_CLK_CGC_ON BIT(4) 83 #define RX_CLK_CGC_ON BIT(5) 84 #define EXT_CLK_CGC_ON BIT(6) 85 #define PROG_RAM_HCLK_OFF BIT(8) 86 #define PROG_RAM_SCLK_OFF BIT(9) 87 #define DEFAULT_CGC_EN GENMASK(6, 0) 88 89 /* GENI_STATUS fields */ 90 #define M_GENI_CMD_ACTIVE BIT(0) 91 #define S_GENI_CMD_ACTIVE BIT(12) 92 93 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ 94 #define SER_CLK_EN BIT(0) 95 #define CLK_DIV_MSK GENMASK(15, 4) 96 #define CLK_DIV_SHFT 4 97 98 /* GENI_IF_DISABLE_RO fields */ 99 #define FIFO_IF_DISABLE (BIT(0)) 100 101 /* GENI_FW_REVISION_RO fields */ 102 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8) 103 #define FW_REV_PROTOCOL_SHFT 8 104 105 /* GENI_CLK_SEL fields */ 106 #define CLK_SEL_MSK GENMASK(2, 0) 107 108 /* SE_GENI_CFG_SEQ_START fields */ 109 #define START_TRIGGER BIT(0) 110 111 /* SE_IRQ_EN fields */ 112 #define DMA_RX_IRQ_EN BIT(0) 113 #define DMA_TX_IRQ_EN BIT(1) 114 #define GENI_M_IRQ_EN BIT(2) 115 #define GENI_S_IRQ_EN BIT(3) 116 117 /* SE_GENI_DMA_MODE_EN */ 118 #define GENI_DMA_MODE_EN BIT(0) 119 120 /* GENI_M_CMD0 fields */ 121 #define M_OPCODE_MSK GENMASK(31, 27) 122 #define M_OPCODE_SHFT 27 123 #define M_PARAMS_MSK GENMASK(26, 0) 124 125 /* GENI_M_CMD_CTRL_REG */ 126 #define M_GENI_CMD_CANCEL BIT(2) 127 #define M_GENI_CMD_ABORT BIT(1) 128 #define M_GENI_DISABLE BIT(0) 129 130 /* GENI_S_CMD0 fields */ 131 #define S_OPCODE_MSK GENMASK(31, 27) 132 #define S_OPCODE_SHFT 27 133 #define S_PARAMS_MSK GENMASK(26, 0) 134 135 /* GENI_S_CMD_CTRL_REG */ 136 #define S_GENI_CMD_CANCEL BIT(2) 137 #define S_GENI_CMD_ABORT BIT(1) 138 #define S_GENI_DISABLE BIT(0) 139 140 /* GENI_M_IRQ_EN fields */ 141 #define M_CMD_DONE_EN BIT(0) 142 #define M_CMD_OVERRUN_EN BIT(1) 143 #define M_ILLEGAL_CMD_EN BIT(2) 144 #define M_CMD_FAILURE_EN BIT(3) 145 #define M_CMD_CANCEL_EN BIT(4) 146 #define M_CMD_ABORT_EN BIT(5) 147 #define M_TIMESTAMP_EN BIT(6) 148 #define M_RX_IRQ_EN BIT(7) 149 #define M_GP_SYNC_IRQ_0_EN BIT(8) 150 #define M_GP_IRQ_0_EN BIT(9) 151 #define M_GP_IRQ_1_EN BIT(10) 152 #define M_GP_IRQ_2_EN BIT(11) 153 #define M_GP_IRQ_3_EN BIT(12) 154 #define M_GP_IRQ_4_EN BIT(13) 155 #define M_GP_IRQ_5_EN BIT(14) 156 #define M_TX_FIFO_NOT_EMPTY_EN BIT(21) 157 #define M_IO_DATA_DEASSERT_EN BIT(22) 158 #define M_IO_DATA_ASSERT_EN BIT(23) 159 #define M_RX_FIFO_RD_ERR_EN BIT(24) 160 #define M_RX_FIFO_WR_ERR_EN BIT(25) 161 #define M_RX_FIFO_WATERMARK_EN BIT(26) 162 #define M_RX_FIFO_LAST_EN BIT(27) 163 #define M_TX_FIFO_RD_ERR_EN BIT(28) 164 #define M_TX_FIFO_WR_ERR_EN BIT(29) 165 #define M_TX_FIFO_WATERMARK_EN BIT(30) 166 #define M_SEC_IRQ_EN BIT(31) 167 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ 168 M_IO_DATA_DEASSERT_EN | \ 169 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ 170 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ 171 M_TX_FIFO_WR_ERR_EN) 172 173 /* GENI_S_IRQ_EN fields */ 174 #define S_CMD_DONE_EN BIT(0) 175 #define S_CMD_OVERRUN_EN BIT(1) 176 #define S_ILLEGAL_CMD_EN BIT(2) 177 #define S_CMD_FAILURE_EN BIT(3) 178 #define S_CMD_CANCEL_EN BIT(4) 179 #define S_CMD_ABORT_EN BIT(5) 180 #define S_GP_SYNC_IRQ_0_EN BIT(8) 181 #define S_GP_IRQ_0_EN BIT(9) 182 #define S_GP_IRQ_1_EN BIT(10) 183 #define S_GP_IRQ_2_EN BIT(11) 184 #define S_GP_IRQ_3_EN BIT(12) 185 #define S_GP_IRQ_4_EN BIT(13) 186 #define S_GP_IRQ_5_EN BIT(14) 187 #define S_IO_DATA_DEASSERT_EN BIT(22) 188 #define S_IO_DATA_ASSERT_EN BIT(23) 189 #define S_RX_FIFO_RD_ERR_EN BIT(24) 190 #define S_RX_FIFO_WR_ERR_EN BIT(25) 191 #define S_RX_FIFO_WATERMARK_EN BIT(26) 192 #define S_RX_FIFO_LAST_EN BIT(27) 193 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ 194 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) 195 196 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ 197 #define WATERMARK_MSK GENMASK(5, 0) 198 199 /* GENI_TX_FIFO_STATUS fields */ 200 #define TX_FIFO_WC GENMASK(27, 0) 201 202 /* GENI_RX_FIFO_STATUS fields */ 203 #define RX_LAST BIT(31) 204 #define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) 205 #define RX_LAST_BYTE_VALID_SHFT 28 206 #define RX_FIFO_WC_MSK GENMASK(24, 0) 207 208 /* SE_GENI_IOS fields */ 209 #define IO2_DATA_IN BIT(1) 210 #define RX_DATA_IN BIT(0) 211 212 /* SE_DMA_TX_IRQ_STAT Register fields */ 213 #define TX_DMA_DONE BIT(0) 214 #define TX_EOT BIT(1) 215 #define TX_SBE BIT(2) 216 #define TX_RESET_DONE BIT(3) 217 218 /* SE_DMA_RX_IRQ_STAT Register fields */ 219 #define RX_DMA_DONE BIT(0) 220 #define RX_EOT BIT(1) 221 #define RX_SBE BIT(2) 222 #define RX_RESET_DONE BIT(3) 223 #define RX_FLUSH_DONE BIT(4) 224 #define RX_DMA_PARITY_ERR BIT(5) 225 #define RX_DMA_BREAK GENMASK(8, 7) 226 #define RX_GENI_GP_IRQ GENMASK(10, 5) 227 #define RX_GENI_CANCEL_IRQ BIT(11) 228 #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) 229 230 /* SE_HW_PARAM_0 fields */ 231 #define TX_FIFO_WIDTH_MSK GENMASK(29, 24) 232 #define TX_FIFO_WIDTH_SHFT 24 233 /* 234 * For QUP HW Version >= 3.10 Tx fifo depth support is increased 235 * to 256bytes and corresponding bits are 16 to 23 236 */ 237 #define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) 238 #define TX_FIFO_DEPTH_MSK GENMASK(21, 16) 239 #define TX_FIFO_DEPTH_SHFT 16 240 241 /* SE_HW_PARAM_1 fields */ 242 #define RX_FIFO_WIDTH_MSK GENMASK(29, 24) 243 #define RX_FIFO_WIDTH_SHFT 24 244 /* 245 * For QUP HW Version >= 3.10 Rx fifo depth support is increased 246 * to 256bytes and corresponding bits are 16 to 23 247 */ 248 #define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) 249 #define RX_FIFO_DEPTH_MSK GENMASK(21, 16) 250 #define RX_FIFO_DEPTH_SHFT 16 251 252 #define HW_VER_MAJOR_MASK GENMASK(31, 28) 253 #define HW_VER_MAJOR_SHFT 28 254 #define HW_VER_MINOR_MASK GENMASK(27, 16) 255 #define HW_VER_MINOR_SHFT 16 256 #define HW_VER_STEP_MASK GENMASK(15, 0) 257 258 #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT) 259 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT) 260 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK) 261 262 /* QUP SE VERSION value for major number 2 and minor number 5 */ 263 #define QUP_SE_VERSION_2_5 0x20050000 264 265 #endif 266