1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * (C) Copyright 2007-2012
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Tom Cubie <tangliang@allwinnertech.com>
6 *
7 * Definitions that are shared between the Allwinner pinctrl and GPIO drivers,
8 * also used by some non-DM SPL code directly.
9 */
10
11 #ifndef _SUNXI_GPIO_H
12 #define _SUNXI_GPIO_H
13
14 #include <linux/types.h>
15
16 #if defined(CONFIG_MACH_SUN9I)
17 #define SUNXI_PIO_BASE 0x06000800
18 #define SUNXI_R_PIO_BASE 0x08002c00
19 #elif defined(CONFIG_SUN50I_GEN_H6)
20 #define SUNXI_PIO_BASE 0x0300b000
21 #define SUNXI_R_PIO_BASE 0x07022000
22 #elif defined(CONFIG_SUNXI_GEN_NCAT2)
23 #define SUNXI_PIO_BASE 0x02000000
24 #define SUNXI_R_PIO_BASE 0x07022000
25 #else
26 #define SUNXI_PIO_BASE 0x01c20800
27 #define SUNXI_R_PIO_BASE 0x01f02c00
28 #endif
29
30 /*
31 * sunxi has 9 banks of gpio, they are:
32 * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
33 * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
34 * PG0 - PG9 | PH0 - PH27 | PI0 - PI12
35 */
36
37 #define SUNXI_GPIO_A 0
38 #define SUNXI_GPIO_B 1
39 #define SUNXI_GPIO_C 2
40 #define SUNXI_GPIO_D 3
41 #define SUNXI_GPIO_E 4
42 #define SUNXI_GPIO_F 5
43 #define SUNXI_GPIO_G 6
44 #define SUNXI_GPIO_H 7
45 #define SUNXI_GPIO_I 8
46
47 /*
48 * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
49 * at a different register offset.
50 *
51 * sun6i has 2 banks:
52 * PL0 - PL8 | PM0 - PM7
53 *
54 * sun8i has 1 bank:
55 * PL0 - PL11
56 *
57 * sun9i has 3 banks:
58 * PL0 - PL9 | PM0 - PM15 | PN0 - PN1
59 */
60 #define SUNXI_GPIO_L 11
61 #define SUNXI_GPIO_M 12
62 #define SUNXI_GPIO_N 13
63
64 #define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
65 #define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
66
67 #define SUNXI_GPIOS_PER_BANK 32
68
69 #define SUNXI_GPIO_NEXT(__gpio) \
70 ((__gpio##_START) + SUNXI_GPIOS_PER_BANK)
71
72 enum sunxi_gpio_number {
73 SUNXI_GPIO_A_START = 0,
74 SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
75 SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
76 SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
77 SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
78 SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
79 SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
80 SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
81 SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
82 SUNXI_GPIO_L_START = 352,
83 SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
84 SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
85 };
86
87 /* SUNXI GPIO number definitions */
88 #define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr))
89 #define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr))
90 #define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr))
91 #define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr))
92 #define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr))
93 #define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr))
94 #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
95 #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
96 #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
97 #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
98 #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
99 #define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
100
101 /* GPIO pin function config */
102 #define SUNXI_GPIO_INPUT 0
103 #define SUNXI_GPIO_OUTPUT 1
104
105 #define SUN8I_H3_GPA_UART0 2
106 #define SUN8I_H3_GPA_UART2 2
107
108 #define SUN4I_GPB_PWM 2
109 #define SUN4I_GPB_TWI0 2
110 #define SUN4I_GPB_TWI1 2
111 #define SUN5I_GPB_TWI1 2
112 #define SUN8I_V3S_GPB_TWI0 2
113 #define SUN4I_GPB_UART0 2
114 #define SUN5I_GPB_UART0 2
115 #define SUN8I_GPB_UART2 2
116 #define SUN8I_A33_GPB_UART0 3
117 #define SUN8I_A83T_GPB_UART0 2
118 #define SUN8I_V3S_GPB_UART0 3
119 #define SUN50I_GPB_UART0 4
120
121 #define SUNXI_GPC_NAND 2
122 #define SUNXI_GPC_SPI0 3
123 #define SUNXI_GPC_SDC2 3
124 #define SUN6I_GPC_SDC3 4
125 #define SUN50I_GPC_SPI0 4
126 #define SUNIV_GPC_SPI0 2
127
128 #define SUNXI_GPD_LCD0 2
129 #define SUNXI_GPD_LVDS0 3
130
131 #define SUNIV_GPE_UART0 5
132
133 #define SUNXI_GPF_SDC0 2
134 #define SUNXI_GPF_UART0 4
135 #define SUN8I_GPF_UART0 3
136
137 #define SUN4I_GPG_SDC1 4
138 #define SUN5I_GPG_SDC1 2
139 #define SUN6I_GPG_SDC1 2
140 #define SUN8I_GPG_SDC1 2
141 #define SUN8I_GPG_UART1 2
142 #define SUN5I_GPG_UART1 4
143
144 #define SUN6I_GPH_PWM 2
145 #define SUN8I_GPH_PWM 2
146 #define SUN4I_GPH_SDC1 5
147 #define SUN6I_GPH_TWI0 2
148 #define SUN8I_GPH_TWI0 2
149 #define SUN50I_GPH_TWI0 2
150 #define SUN6I_GPH_TWI1 2
151 #define SUN8I_GPH_TWI1 2
152 #define SUN50I_GPH_TWI1 2
153 #define SUN6I_GPH_UART0 2
154 #define SUN9I_GPH_UART0 2
155 #define SUN50I_H6_GPH_UART0 2
156 #define SUN50I_H616_GPH_UART0 2
157
158 #define SUNXI_GPI_SDC3 2
159
160 #define SUN6I_GPL0_R_P2WI_SCK 3
161 #define SUN6I_GPL1_R_P2WI_SDA 3
162
163 #define SUN8I_GPL_R_RSB 2
164 #define SUN8I_H3_GPL_R_TWI 2
165 #define SUN8I_A23_GPL_R_TWI 3
166 #define SUN8I_GPL_R_UART 2
167 #define SUN50I_GPL_R_TWI 2
168 #define SUN50I_H616_GPL_R_TWI 3
169
170 #define SUN9I_GPN_R_RSB 3
171
172 #ifdef CONFIG_SUNXI_NEW_PINCTRL
173 #define SUNXI_PINCTRL_BANK_SIZE 0x30
174 #define SUNXI_GPIO_DISABLE 0xf
175 #else
176 #define SUNXI_PINCTRL_BANK_SIZE 0x24
177 #define SUNXI_GPIO_DISABLE 0x7
178 #endif
179
180 /* GPIO pin pull-up/down config */
181 #define SUNXI_GPIO_PULL_DISABLE 0
182 #define SUNXI_GPIO_PULL_UP 1
183 #define SUNXI_GPIO_PULL_DOWN 2
184
185 struct sunxi_gpio_plat {
186 void *regs;
187 char bank_name[3];
188 };
189
190 /* prototypes for the non-DM GPIO/pinctrl functions, used in the SPL */
191 void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val);
192 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
193 int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset);
194 int sunxi_gpio_get_cfgpin(u32 pin);
195 void sunxi_gpio_set_drv(u32 pin, u32 val);
196 void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val);
197 void sunxi_gpio_set_pull(u32 pin, u32 val);
198 void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val);
199 int sunxi_name_to_gpio(const char *name);
200
201 #if !defined CONFIG_XPL_BUILD && defined CONFIG_AXP_GPIO
202 int axp_gpio_init(void);
203 #else
axp_gpio_init(void)204 static inline int axp_gpio_init(void) { return 0; }
205 #endif
206
207 #endif /* _SUNXI_GPIO_H */
208