1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Defines APIs and structures that allow software to interact with a 4 * TPM2 device 5 * 6 * Copyright (c) 2020 Linaro 7 * Copyright (c) 2018 Bootlin 8 * 9 * The structures are described in 10 * Trusted Platform Module Library Part 2: Structures 11 * http://tcg.tjn.chef.causewaynow.com/resource/tpm-library-specification/ 12 * 13 * C header files are listed in 14 * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/ 15 * 16 * Author: Miquel Raynal <miquel.raynal@bootlin.com> 17 */ 18 19 #ifndef __TPM_V2_H 20 #define __TPM_V2_H 21 22 #include <tpm-common.h> 23 #include <linux/errno.h> 24 25 struct udevice; 26 27 #define TPM2_DIGEST_LEN 32 28 29 #define TPM2_SHA1_DIGEST_SIZE 20 30 #define TPM2_SHA256_DIGEST_SIZE 32 31 #define TPM2_SHA384_DIGEST_SIZE 48 32 #define TPM2_SHA512_DIGEST_SIZE 64 33 #define TPM2_SM3_256_DIGEST_SIZE 32 34 35 #define TPM2_MAX_PCRS 32 36 #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8) 37 #define TPM2_MAX_CAP_BUFFER 1024 38 #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \ 39 sizeof(u32)) / sizeof(struct tpms_tagged_property)) 40 41 #define TPM2_HDR_LEN 10 42 43 #define TPM2_CAP_PCRS 0x00000005U 44 #define TPM2_CAP_TPM_PROPERTIES 0x00000006U 45 46 /* Definition of (UINT32) TPM2_PT Constants */ 47 #define TPM2_PT_GROUP (u32)(0x00000100) 48 #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1) 49 #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5) 50 #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18) 51 #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30) 52 #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31) 53 54 /** 55 * struct tpms_tagged_property - TPMS_TAGGED_PROPERTY structure 56 * 57 * This structure is returned by TPM2_GetCapability() to report 58 * a u32 property value. 59 * 60 * @property: property identifier 61 * @value: value of the property 62 */ 63 struct tpms_tagged_property { 64 u32 property; 65 u32 value; 66 } __packed; 67 68 /** 69 * struct tpms_pcr_selection - TPMS_PCR_SELECTION structure 70 * 71 * This structure allows to specify a hash algorithm and a list of 72 * selected PCRs. A PCR is selected by setting the related bit in 73 * @pcr_select to 1. 74 * 75 * @hash: hash algorithm associated with the selection 76 * @size_of_select: size in bytes of the @pcr_select array 77 * @pcr_select: bit map of selected PCRs 78 */ 79 struct tpms_pcr_selection { 80 u16 hash; 81 u8 size_of_select; 82 u8 pcr_select[TPM2_PCR_SELECT_MAX]; 83 } __packed; 84 85 /** 86 * struct tpml_pcr_selection - TPML_PCR_SELECTION structure 87 * 88 * @count: number of selection structures, may be zero 89 * @selection: list of selections 90 */ 91 struct tpml_pcr_selection { 92 u32 count; 93 struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS]; 94 } __packed; 95 96 /* TPML_TAGGED_TPM_PROPERTY Structure */ 97 struct tpml_tagged_tpm_property { 98 u32 count; 99 struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES]; 100 } __packed; 101 102 /* TPMU_CAPABILITIES Union */ 103 union tpmu_capabilities { 104 /* 105 * Non exhaustive. Only added the structs needed for our 106 * current code 107 */ 108 struct tpml_pcr_selection assigned_pcr; 109 struct tpml_tagged_tpm_property tpm_properties; 110 } __packed; 111 112 /* TPMS_CAPABILITY_DATA Structure */ 113 struct tpms_capability_data { 114 u32 capability; 115 union tpmu_capabilities data; 116 } __packed; 117 118 /** 119 * Definition of TPMU_HA Union 120 */ 121 union tpmu_ha { 122 u8 sha1[TPM2_SHA1_DIGEST_SIZE]; 123 u8 sha256[TPM2_SHA256_DIGEST_SIZE]; 124 u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE]; 125 u8 sha384[TPM2_SHA384_DIGEST_SIZE]; 126 u8 sha512[TPM2_SHA512_DIGEST_SIZE]; 127 } __packed; 128 129 /** 130 * Definition of TPMT_HA Structure 131 * 132 * @hash_alg: Hash algorithm defined in enum tpm2_algorithms 133 * @digest: Digest value for a given algorithm 134 */ 135 struct tpmt_ha { 136 u16 hash_alg; 137 union tpmu_ha digest; 138 } __packed; 139 140 /** 141 * Definition of TPML_DIGEST_VALUES Structure 142 * 143 * @count: Number of algorithms supported by hardware 144 * @digests: struct for algorithm id and hash value 145 */ 146 struct tpml_digest_values { 147 u32 count; 148 struct tpmt_ha digests[TPM2_NUM_PCR_BANKS]; 149 } __packed; 150 151 /** 152 * TPM2 Structure Tags for command/response buffers. 153 * 154 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication. 155 * @TPM2_ST_SESSIONS: the command needs an authentication. 156 */ 157 enum tpm2_structures { 158 TPM2_ST_NO_SESSIONS = 0x8001, 159 TPM2_ST_SESSIONS = 0x8002, 160 }; 161 162 /** 163 * TPM2 type of boolean. 164 */ 165 enum tpm2_yes_no { 166 TPMI_YES = 1, 167 TPMI_NO = 0, 168 }; 169 170 /** 171 * TPM2 startup values. 172 * 173 * @TPM2_SU_CLEAR: reset the internal state. 174 * @TPM2_SU_STATE: restore saved state (if any). 175 */ 176 enum tpm2_startup_types { 177 TPM2_SU_CLEAR = 0x0000, 178 TPM2_SU_STATE = 0x0001, 179 }; 180 181 /** 182 * TPM2 permanent handles. 183 * 184 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy. 185 * @TPM2_RS_PW: indicates a password. 186 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy. 187 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy. 188 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy. 189 */ 190 enum tpm2_handles { 191 TPM2_RH_OWNER = 0x40000001, 192 TPM2_RS_PW = 0x40000009, 193 TPM2_RH_LOCKOUT = 0x4000000A, 194 TPM2_RH_ENDORSEMENT = 0x4000000B, 195 TPM2_RH_PLATFORM = 0x4000000C, 196 }; 197 198 /** 199 * TPM2 command codes used at the beginning of a buffer, gives the command. 200 * 201 * @TPM2_CC_STARTUP: TPM2_Startup(). 202 * @TPM2_CC_SELF_TEST: TPM2_SelfTest(). 203 * @TPM2_CC_CLEAR: TPM2_Clear(). 204 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl(). 205 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth(). 206 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy(). 207 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset(). 208 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters(). 209 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility(). 210 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom(). 211 * @TPM2_CC_PCR_READ: TPM2_PCR_Read(). 212 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend(). 213 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue(). 214 */ 215 enum tpm2_command_codes { 216 TPM2_CC_STARTUP = 0x0144, 217 TPM2_CC_SELF_TEST = 0x0143, 218 TPM2_CC_HIER_CONTROL = 0x0121, 219 TPM2_CC_CLEAR = 0x0126, 220 TPM2_CC_CLEARCONTROL = 0x0127, 221 TPM2_CC_HIERCHANGEAUTH = 0x0129, 222 TPM2_CC_NV_DEFINE_SPACE = 0x012a, 223 TPM2_CC_PCR_SETAUTHPOL = 0x012C, 224 TPM2_CC_NV_WRITE = 0x0137, 225 TPM2_CC_NV_WRITELOCK = 0x0138, 226 TPM2_CC_DAM_RESET = 0x0139, 227 TPM2_CC_DAM_PARAMETERS = 0x013A, 228 TPM2_CC_NV_READ = 0x014E, 229 TPM2_CC_GET_CAPABILITY = 0x017A, 230 TPM2_CC_GET_RANDOM = 0x017B, 231 TPM2_CC_PCR_READ = 0x017E, 232 TPM2_CC_PCR_EXTEND = 0x0182, 233 TPM2_CC_PCR_SETAUTHVAL = 0x0183, 234 TPM2_CC_PCR_ALLOCATE = 0x012B, 235 TPM2_CC_SHUTDOWN = 0x0145, 236 }; 237 238 /** 239 * TPM2 return codes. 240 */ 241 enum tpm2_return_codes { 242 TPM2_RC_SUCCESS = 0x0000, 243 TPM2_RC_BAD_TAG = 0x001E, 244 TPM2_RC_FMT1 = 0x0080, 245 TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003, 246 TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004, 247 TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015, 248 TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022, 249 TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B, 250 TPM2_RC_VER1 = 0x0100, 251 TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000, 252 TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001, 253 TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020, 254 TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025, 255 TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043, 256 TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044, 257 TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045, 258 TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c, 259 TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053, 260 TPM2_RC_WARN = 0x0900, 261 TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A, 262 TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010, 263 TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021, 264 }; 265 266 /** 267 * TPM2 algorithms. 268 */ 269 enum tpm2_algorithms { 270 TPM2_ALG_INVAL = -EINVAL, 271 TPM2_ALG_SHA1 = 0x04, 272 TPM2_ALG_XOR = 0x0A, 273 TPM2_ALG_SHA256 = 0x0B, 274 TPM2_ALG_SHA384 = 0x0C, 275 TPM2_ALG_SHA512 = 0x0D, 276 TPM2_ALG_NULL = 0x10, 277 TPM2_ALG_SM3_256 = 0x12, 278 }; 279 280 /** 281 * struct digest_info - details of supported digests 282 * 283 * @hash_name: hash name 284 * @hash_alg: hash algorithm id 285 * @hash_mask: hash registry mask 286 * @hash_len: hash digest length 287 */ 288 struct digest_info { 289 const char *hash_name; 290 u16 hash_alg; 291 u32 hash_mask; 292 u16 hash_len; 293 bool supported; 294 }; 295 296 /* Algorithm Registry */ 297 #define TCG2_BOOT_HASH_ALG_SHA1 0x00000001 298 #define TCG2_BOOT_HASH_ALG_SHA256 0x00000002 299 #define TCG2_BOOT_HASH_ALG_SHA384 0x00000004 300 #define TCG2_BOOT_HASH_ALG_SHA512 0x00000008 301 #define TCG2_BOOT_HASH_ALG_SM3_256 0x00000010 302 303 static const struct digest_info hash_algo_list[] = { 304 { 305 "sha1", 306 TPM2_ALG_SHA1, 307 TCG2_BOOT_HASH_ALG_SHA1, 308 TPM2_SHA1_DIGEST_SIZE, 309 #if IS_ENABLED(CONFIG_SHA1) 310 true, 311 #else 312 false, 313 #endif 314 }, 315 { 316 "sha256", 317 TPM2_ALG_SHA256, 318 TCG2_BOOT_HASH_ALG_SHA256, 319 TPM2_SHA256_DIGEST_SIZE, 320 #if IS_ENABLED(CONFIG_SHA256) 321 true, 322 #else 323 false, 324 #endif 325 }, 326 { 327 "sha384", 328 TPM2_ALG_SHA384, 329 TCG2_BOOT_HASH_ALG_SHA384, 330 TPM2_SHA384_DIGEST_SIZE, 331 #if IS_ENABLED(CONFIG_SHA384) 332 true, 333 #else 334 false, 335 #endif 336 }, 337 { 338 "sha512", 339 TPM2_ALG_SHA512, 340 TCG2_BOOT_HASH_ALG_SHA512, 341 TPM2_SHA512_DIGEST_SIZE, 342 #if IS_ENABLED(CONFIG_SHA512) 343 true, 344 #else 345 false, 346 #endif 347 }, 348 }; 349 350 /* NV index attributes */ 351 enum tpm_index_attrs { 352 TPMA_NV_PPWRITE = 1UL << 0, 353 TPMA_NV_OWNERWRITE = 1UL << 1, 354 TPMA_NV_AUTHWRITE = 1UL << 2, 355 TPMA_NV_POLICYWRITE = 1UL << 3, 356 TPMA_NV_COUNTER = 1UL << 4, 357 TPMA_NV_BITS = 1UL << 5, 358 TPMA_NV_EXTEND = 1UL << 6, 359 TPMA_NV_POLICY_DELETE = 1UL << 10, 360 TPMA_NV_WRITELOCKED = 1UL << 11, 361 TPMA_NV_WRITEALL = 1UL << 12, 362 TPMA_NV_WRITEDEFINE = 1UL << 13, 363 TPMA_NV_WRITE_STCLEAR = 1UL << 14, 364 TPMA_NV_GLOBALLOCK = 1UL << 15, 365 TPMA_NV_PPREAD = 1UL << 16, 366 TPMA_NV_OWNERREAD = 1UL << 17, 367 TPMA_NV_AUTHREAD = 1UL << 18, 368 TPMA_NV_POLICYREAD = 1UL << 19, 369 TPMA_NV_NO_DA = 1UL << 25, 370 TPMA_NV_ORDERLY = 1UL << 26, 371 TPMA_NV_CLEAR_STCLEAR = 1UL << 27, 372 TPMA_NV_READLOCKED = 1UL << 28, 373 TPMA_NV_WRITTEN = 1UL << 29, 374 TPMA_NV_PLATFORMCREATE = 1UL << 30, 375 TPMA_NV_READ_STCLEAR = 1UL << 31, 376 377 TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD | 378 TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD, 379 TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE | 380 TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE, 381 }; 382 383 enum { 384 TPM_ACCESS_VALID = 1 << 7, 385 TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5, 386 TPM_ACCESS_REQUEST_PENDING = 1 << 2, 387 TPM_ACCESS_REQUEST_USE = 1 << 1, 388 TPM_ACCESS_ESTABLISHMENT = 1 << 0, 389 }; 390 391 enum { 392 TPM_STS_FAMILY_SHIFT = 26, 393 TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT, 394 TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT, 395 TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25, 396 TPM_STS_COMMAND_CANCEL = 1 << 24, 397 TPM_STS_BURST_COUNT_SHIFT = 8, 398 TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT, 399 TPM_STS_VALID = 1 << 7, 400 TPM_STS_COMMAND_READY = 1 << 6, 401 TPM_STS_GO = 1 << 5, 402 TPM_STS_DATA_AVAIL = 1 << 4, 403 TPM_STS_DATA_EXPECT = 1 << 3, 404 TPM_STS_SELF_TEST_DONE = 1 << 2, 405 TPM_STS_RESPONSE_RETRY = 1 << 1, 406 TPM_STS_READ_ZERO = 0x23 407 }; 408 409 enum { 410 TPM_CMD_COUNT_OFFSET = 2, 411 TPM_CMD_ORDINAL_OFFSET = 6, 412 TPM_MAX_BUF_SIZE = 1260, 413 }; 414 415 enum { 416 /* Secure storage for firmware settings */ 417 TPM_HT_PCR = 0, 418 TPM_HT_NV_INDEX, 419 TPM_HT_HMAC_SESSION, 420 TPM_HT_POLICY_SESSION, 421 422 HR_SHIFT = 24, 423 HR_PCR = TPM_HT_PCR << HR_SHIFT, 424 HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT, 425 HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT, 426 HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT, 427 }; 428 429 /** 430 * Issue a TPM2_Startup command. 431 * 432 * @dev TPM device 433 * @mode TPM startup mode 434 * 435 * Return: code of the operation 436 */ 437 u32 tpm2_startup(struct udevice *dev, bool onoff, enum tpm2_startup_types mode); 438 439 /** 440 * Issue a TPM2_SelfTest command. 441 * 442 * @dev TPM device 443 * @full_test Asking to perform all tests or only the untested ones 444 * 445 * Return: code of the operation 446 */ 447 u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test); 448 449 /** 450 * Issue a TPM2_Clear command. 451 * 452 * @dev TPM device 453 * @handle Handle 454 * @pw Password 455 * @pw_sz Length of the password 456 * 457 * Return: code of the operation 458 */ 459 u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw, 460 const ssize_t pw_sz); 461 462 /** 463 * Issue a TPM_NV_DefineSpace command 464 * 465 * This allows a space to be defined with given attributes and policy 466 * 467 * @dev TPM device 468 * @space_index index of the area 469 * @space_size size of area in bytes 470 * @nv_attributes TPM_NV_ATTRIBUTES of the area 471 * @nv_policy policy to use 472 * @nv_policy_size size of the policy 473 * Return: return code of the operation 474 */ 475 u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index, 476 size_t space_size, u32 nv_attributes, 477 const u8 *nv_policy, size_t nv_policy_size); 478 479 /** 480 * Issue a TPM2_PCR_Extend command. 481 * 482 * @dev TPM device 483 * @index Index of the PCR 484 * @algorithm Algorithm used, defined in 'enum tpm2_algorithms' 485 * @digest Value representing the event to be recorded 486 * @digest_len len of the hash 487 * 488 * Return: code of the operation 489 */ 490 u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm, 491 const u8 *digest, u32 digest_len); 492 493 /** 494 * Read data from the secure storage 495 * 496 * @dev TPM device 497 * @index Index of data to read 498 * @data Place to put data 499 * @count Number of bytes of data 500 * Return: code of the operation 501 */ 502 u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count); 503 504 /** 505 * Write data to the secure storage 506 * 507 * @dev TPM device 508 * @index Index of data to write 509 * @data Data to write 510 * @count Number of bytes of data 511 * Return: code of the operation 512 */ 513 u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data, 514 u32 count); 515 516 /** 517 * Issue a TPM2_PCR_Read command. 518 * 519 * @dev TPM device 520 * @idx Index of the PCR 521 * @idx_min_sz Minimum size in bytes of the pcrSelect array 522 * @algorithm Algorithm used, defined in 'enum tpm2_algorithms' 523 * @data Output buffer for contents of the named PCR 524 * @digest_len len of the data 525 * @updates Optional out parameter: number of updates for this PCR 526 * 527 * Return: code of the operation 528 */ 529 u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz, 530 u16 algorithm, void *data, u32 digest_len, 531 unsigned int *updates); 532 533 /** 534 * Issue a TPM2_GetCapability command. This implementation is limited 535 * to query property index that is 4-byte wide. 536 * 537 * @dev TPM device 538 * @capability Partition of capabilities 539 * @property Further definition of capability, limited to be 4 bytes wide 540 * @buf Output buffer for capability information 541 * @prop_count Size of output buffer 542 * 543 * Return: code of the operation 544 */ 545 u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property, 546 void *buf, size_t prop_count); 547 548 /** 549 * tpm2_get_pcr_info() - get the supported, active PCRs and number of banks 550 * 551 * @dev: TPM device 552 * @pcrs: struct tpml_pcr_selection of available PCRs 553 * 554 * @return 0 on success, code of operation or negative errno on failure 555 */ 556 int tpm2_get_pcr_info(struct udevice *dev, struct tpml_pcr_selection *pcrs); 557 558 /** 559 * Issue a TPM2_DictionaryAttackLockReset command. 560 * 561 * @dev TPM device 562 * @pw Password 563 * @pw_sz Length of the password 564 * 565 * Return: code of the operation 566 */ 567 u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz); 568 569 /** 570 * Issue a TPM2_DictionaryAttackParameters command. 571 * 572 * @dev TPM device 573 * @pw Password 574 * @pw_sz Length of the password 575 * @max_tries Count of authorizations before lockout 576 * @recovery_time Time before decrementation of the failure count 577 * @lockout_recovery Time to wait after a lockout 578 * 579 * Return: code of the operation 580 */ 581 u32 tpm2_dam_parameters(struct udevice *dev, const char *pw, 582 const ssize_t pw_sz, unsigned int max_tries, 583 unsigned int recovery_time, 584 unsigned int lockout_recovery); 585 586 /** 587 * Issue a TPM2_HierarchyChangeAuth command. 588 * 589 * @dev TPM device 590 * @handle Handle 591 * @newpw New password 592 * @newpw_sz Length of the new password 593 * @oldpw Old password 594 * @oldpw_sz Length of the old password 595 * 596 * Return: code of the operation 597 */ 598 int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw, 599 const ssize_t newpw_sz, const char *oldpw, 600 const ssize_t oldpw_sz); 601 602 /** 603 * Issue a TPM_PCR_SetAuthPolicy command. 604 * 605 * @dev TPM device 606 * @pw Platform password 607 * @pw_sz Length of the password 608 * @index Index of the PCR 609 * @digest New key to access the PCR 610 * 611 * Return: code of the operation 612 */ 613 u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw, 614 const ssize_t pw_sz, u32 index, const char *key); 615 616 /** 617 * Issue a TPM_PCR_SetAuthValue command. 618 * 619 * @dev TPM device 620 * @pw Platform password 621 * @pw_sz Length of the password 622 * @index Index of the PCR 623 * @digest New key to access the PCR 624 * @key_sz Length of the new key 625 * 626 * Return: code of the operation 627 */ 628 u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw, 629 const ssize_t pw_sz, u32 index, const char *key, 630 const ssize_t key_sz); 631 632 /** 633 * Issue a TPM2_GetRandom command. 634 * 635 * @dev TPM device 636 * @param data output buffer for the random bytes 637 * @param count size of output buffer 638 * 639 * Return: return code of the operation 640 */ 641 u32 tpm2_get_random(struct udevice *dev, void *data, u32 count); 642 643 /** 644 * Lock data in the TPM 645 * 646 * Once locked the data cannot be written until after a reboot 647 * 648 * @dev TPM device 649 * @index Index of data to lock 650 * Return: code of the operation 651 */ 652 u32 tpm2_write_lock(struct udevice *dev, u32 index); 653 654 /** 655 * Disable access to any platform data 656 * 657 * This can be called to close off access to the firmware data in the data, 658 * before calling the kernel. 659 * 660 * @dev TPM device 661 * Return: code of the operation 662 */ 663 u32 tpm2_disable_platform_hierarchy(struct udevice *dev); 664 665 /** 666 * submit user specified data to the TPM and get response 667 * 668 * @dev TPM device 669 * @sendbuf: Buffer of the data to send 670 * @recvbuf: Buffer to save the response to 671 * @recv_size: Pointer to the size of the response buffer 672 * 673 * Return: code of the operation 674 */ 675 u32 tpm2_submit_command(struct udevice *dev, const u8 *sendbuf, 676 u8 *recvbuf, size_t *recv_size); 677 678 /** 679 * tpm_cr50_report_state() - Report the Cr50 internal state 680 * 681 * @dev: TPM device 682 * @vendor_cmd: Vendor command number to send 683 * @vendor_subcmd: Vendor sub-command number to send 684 * @recvbuf: Buffer to save the response to 685 * @recv_size: Pointer to the size of the response buffer 686 * Return: result of the operation 687 */ 688 u32 tpm2_report_state(struct udevice *dev, uint vendor_cmd, uint vendor_subcmd, 689 u8 *recvbuf, size_t *recv_size); 690 691 /** 692 * tpm2_enable_nvcommits() - Tell TPM to commit NV data immediately 693 * 694 * For Chromium OS verified boot, we may reboot or reset at different times, 695 * possibly leaving non-volatile data unwritten by the TPM. 696 * 697 * This vendor command is used to indicate that non-volatile data should be 698 * written to its store immediately. 699 * 700 * @dev TPM device 701 * @vendor_cmd: Vendor command number to send 702 * @vendor_subcmd: Vendor sub-command number to send 703 * Return: result of the operation 704 */ 705 u32 tpm2_enable_nvcommits(struct udevice *dev, uint vendor_cmd, 706 uint vendor_subcmd); 707 708 /** 709 * tpm2_scan_masks - Scan the bitmask of algorithms based on the 710 * active/supported banks and the one from eventlog. 711 * 712 * @dev TPM device 713 * @log_active Active algorithm bitmask 714 * @mask Bitmask to set 715 * 716 * Return: zero on success, negative errno otherwise 717 */ 718 int tpm2_scan_masks(struct udevice *dev, u32 log_active, u32 *mask); 719 720 /** 721 * tpm2_pcr_config_algo() - Allocate the active PCRs. Requires reboot 722 * 723 * @dev TPM device 724 * @algo_mask Mask of the algorithms 725 * @pcr PCR structure for allocation 726 * @pcr_len Actual PCR data length 727 * 728 * Return: code of the operation 729 */ 730 u32 tpm2_pcr_config_algo(struct udevice *dev, u32 algo_mask, 731 struct tpml_pcr_selection *pcr, u32 *pcr_len); 732 733 /** 734 * tpm2_send_pcr_allocate() - Send PCR allocate command. Requires reboot 735 * 736 * @dev TPM device 737 * @pw Platform password 738 * @pw_sz Length of the password 739 * @pcr PCR structure for allocation 740 * @pcr_len Actual PCR data length 741 * 742 * Return: code of the operation 743 */ 744 u32 tpm2_send_pcr_allocate(struct udevice *dev, const char *pw, 745 const ssize_t pw_sz, struct tpml_pcr_selection *pcr, 746 u32 pcr_len); 747 /** 748 * tpm2_activate_banks() - Activate PCR banks 749 * 750 * @param dev TPM device 751 * @log_active Bitmask of eventlog algorithms 752 * 753 * Return: code of the operation 754 */ 755 int tpm2_activate_banks(struct udevice *dev, u32 log_active); 756 757 /** 758 * tpm2_auto_start() - start up the TPM and perform selftests. 759 * If a testable function has not been tested and is 760 * requested the TPM2 will return TPM_RC_NEEDS_TEST. 761 * 762 * @param dev TPM device 763 * Return: TPM2_RC_TESTING, if TPM2 self-test is in progress. 764 * TPM2_RC_SUCCESS, if testing of all functions is complete without 765 * functional failures. 766 * TPM2_RC_FAILURE, if any test failed. 767 * TPM2_RC_INITIALIZE, if the TPM has not gone through the Startup 768 * sequence 769 770 */ 771 u32 tpm2_auto_start(struct udevice *dev); 772 773 /** 774 * tpm2_name_to_algorithm() - Return an algorithm id given a supported 775 * algorithm name 776 * 777 * @name: algorithm name 778 * Return: enum tpm2_algorithms or -EINVAL 779 */ 780 enum tpm2_algorithms tpm2_name_to_algorithm(const char *name); 781 782 /** 783 * tpm2_algorithm_name() - Return an algorithm name string for a 784 * supported algorithm id 785 * 786 * @algorithm_id: algorithm defined in enum tpm2_algorithms 787 * Return: algorithm name string or "" 788 */ 789 const char *tpm2_algorithm_name(enum tpm2_algorithms); 790 791 /** 792 * tpm2_algorithm_supported() - Check if the algorithm supported by U-Boot 793 * 794 * @algorithm_id: algorithm defined in enum tpm2_algorithms 795 * Return: true if supported, otherwise false 796 */ 797 bool tpm2_algorithm_supported(enum tpm2_algorithms algo); 798 799 /** 800 * tpm2_algorithm_to_len() - Return an algorithm length for supported algorithm id 801 * 802 * @algorithm_id: algorithm defined in enum tpm2_algorithms 803 * Return: len or 0 if not supported 804 */ 805 u16 tpm2_algorithm_to_len(enum tpm2_algorithms algo); 806 807 /* 808 * When measured boot is enabled via EFI or bootX commands all the algorithms 809 * above are selected by our Kconfigs. Due to U-Boots nature of being small there 810 * are cases where we need some functionality from the TPM -- e.g storage or RNG 811 * but we don't want to support measurements. 812 * 813 * The choice of hash algorithms are determined by the platform and the TPM 814 * configuration. Failing to cap a PCR in a bank which the platform left 815 * active is a security vulnerability. It permits the unsealing of secrets 816 * if an attacker can replay a good set of measurements into an unused bank. 817 * 818 * On top of that a previous stage bootloader (e.g TF-A), migh pass an eventlog 819 * since it doesn't have a TPM driver, which U-Boot needs to replace. The algorit h 820 * choice is a compile time option in that case and we need to make sure we conform. 821 * 822 * Add a variable here that sums the supported algorithms U-Boot was compiled 823 * with so we can refuse to do measurements if we don't support all of them 824 */ 825 826 /** 827 * tpm2_check_active_banks() - Check if the active PCR banks are supported by 828 * our configuration 829 * 830 * @dev: TPM device 831 * Return: true if allowed 832 */ 833 bool tpm2_check_active_banks(struct udevice *dev); 834 835 /** 836 * tpm2_is_active_bank() - check the pcr_select. If at least one of the PCRs 837 * supports the algorithm add it on the active ones 838 * 839 * @selection: PCR selection structure 840 * Return: True if the algorithm is active 841 */ 842 bool tpm2_is_active_bank(struct tpms_pcr_selection *selection); 843 844 /** 845 * tpm2_print_active_banks() - Print the active TPM PCRs 846 * 847 * @dev: TPM device 848 */ 849 void tpm2_print_active_banks(struct udevice *dev); 850 851 #endif /* __TPM_V2_H */ 852