1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013, 2015 Freescale Semiconductor, Inc. 4 * 5 * Driver for the Vitesse VSC9953 L2 Switch 6 */ 7 8 #ifndef _VSC9953_H_ 9 #define _VSC9953_H_ 10 11 #include <asm/types.h> 12 #include <linux/bitops.h> 13 14 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) 15 16 #define VSC9953_SYS_OFFSET 0x010000 17 #define VSC9953_REW_OFFSET 0x030000 18 #define VSC9953_DEV_GMII_OFFSET 0x100000 19 #define VSC9953_QSYS_OFFSET 0x200000 20 #define VSC9953_ANA_OFFSET 0x280000 21 #define VSC9953_DEVCPU_GCB 0x070000 22 #define VSC9953_ES0 0x040000 23 #define VSC9953_IS1 0x050000 24 #define VSC9953_IS2 0x060000 25 26 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 27 #define VSC9953_PHY_REGS_OFFST 0x0000AC 28 29 /* Macros for vsc9953_chip_regs.soft_rst register */ 30 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 31 32 /* Macros for vsc9953_sys_sys.reset_cfg register */ 33 #define VSC9953_CORE_ENABLE 0x80 34 #define VSC9953_MEM_ENABLE 0x40 35 #define VSC9953_MEM_INIT 0x20 36 37 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ 38 #define VSC9953_MAC_ENA_CFG 0x00000011 39 40 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ 41 #define VSC9953_MAC_MODE_CFG 0x00000011 42 43 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ 44 #define VSC9953_MAC_IFG_CFG 0x00000515 45 46 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ 47 #define VSC9953_MAC_HDX_CFG 0x00001043 48 49 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ 50 #define VSC9953_MAC_MAX_LEN 0x000005ee 51 52 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ 53 #define VSC9953_CLOCK_CFG 0x00000001 54 #define VSC9953_CLOCK_CFG_1000M 0x00000001 55 56 /* Macros for vsc9953_sys_sys.front_port_mode register */ 57 #define VSC9953_FRONT_PORT_MODE 0x00000000 58 59 /* Macros for vsc9953_ana_pfc.pfc_cfg register */ 60 #define VSC9953_PFC_FC 0x00000001 61 #define VSC9953_PFC_FC_QSGMII 0x00000000 62 63 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ 64 #define VSC9953_MAC_FC_CFG 0x04700000 65 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 66 67 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ 68 #define VSC9953_PAUSE_CFG 0x001ffffe 69 70 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ 71 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff 72 73 /* Macros for vsc9953_sys_sys.stat_cfg register */ 74 #define VSC9953_STAT_CLEAR_RX 0x00000400 75 #define VSC9953_STAT_CLEAR_TX 0x00000800 76 #define VSC9953_STAT_CLEAR_DR 0x00001000 77 78 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ 79 #define VSC9953_VCAP_MV_CFG 0x0000ffff 80 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 81 82 /* Macros for register vsc9953_ana_ana_tables.mac_access register */ 83 #define VSC9953_MAC_CMD_IDLE 0x00000000 84 #define VSC9953_MAC_CMD_LEARN 0x00000001 85 #define VSC9953_MAC_CMD_FORGET 0x00000002 86 #define VSC9953_MAC_CMD_AGE 0x00000003 87 #define VSC9953_MAC_CMD_NEXT 0x00000004 88 #define VSC9953_MAC_CMD_READ 0x00000006 89 #define VSC9953_MAC_CMD_WRITE 0x00000007 90 #define VSC9953_MAC_CMD_MASK 0x00000007 91 #define VSC9953_MAC_CMD_VALID 0x00000800 92 #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000 93 #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200 94 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400 95 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600 96 #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600 97 #define VSC9953_MAC_DESTIDX_MASK 0x000001f8 98 #define VSC9953_MAC_VID_MASK 0x1fff0000 99 #define VSC9953_MAC_MACH_MASK 0x0000ffff 100 101 /* Macros for vsc9953_ana_port.vlan_cfg register */ 102 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 103 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 104 #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000 105 #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000 106 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff 107 108 /* Macros for vsc9953_rew_port.port_vlan_cfg register */ 109 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff 110 111 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ 112 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff 113 114 /* Macros for vsc9953_ana_ana_tables.vlan_access register */ 115 #define VSC9953_VLAN_PORT_MASK 0x00001ffc 116 #define VSC9953_VLAN_CMD_MASK 0x00000003 117 #define VSC9953_VLAN_CMD_IDLE 0x00000000 118 #define VSC9953_VLAN_CMD_READ 0x00000001 119 #define VSC9953_VLAN_CMD_WRITE 0x00000002 120 #define VSC9953_VLAN_CMD_INIT 0x00000003 121 122 /* Macros for vsc9953_ana_port.port_cfg register */ 123 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080 124 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 125 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 126 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 127 #define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c 128 129 /* Macros for vsc9953_qsys_sys.switch_port_mode register */ 130 #define VSC9953_PORT_ENA 0x00002000 131 132 /* Macros for vsc9953_ana_ana.agen_ctrl register */ 133 #define VSC9953_FID_MASK_ALL 0x00fff000 134 135 /* Macros for vsc9953_ana_ana.adv_learn register */ 136 #define VSC9953_VLAN_CHK 0x00000400 137 138 /* Macros for vsc9953_ana_ana.auto_age register */ 139 #define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe 140 141 /* Macros for vsc9953_rew_port.port_tag_cfg register */ 142 #define VSC9953_TAG_CFG_MASK 0x00000180 143 #define VSC9953_TAG_CFG_NONE 0x00000000 144 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 145 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 146 #define VSC9953_TAG_CFG_ALL 0x00000180 147 #define VSC9953_TAG_VID_PVID 0x00000010 148 149 /* Macros for vsc9953_ana_ana.anag_efil register */ 150 #define VSC9953_AGE_PORT_EN 0x00080000 151 #define VSC9953_AGE_PORT_MASK 0x0007c000 152 #define VSC9953_AGE_VID_EN 0x00002000 153 #define VSC9953_AGE_VID_MASK 0x00001fff 154 155 /* Macros for vsc9953_ana_ana_tables.mach_data register */ 156 #define VSC9953_MACHDATA_VID_MASK 0x1fff0000 157 158 /* Macros for vsc9953_ana_common.aggr_cfg register */ 159 #define VSC9953_AC_RND_ENA 0x00000080 160 #define VSC9953_AC_DMAC_ENA 0x00000040 161 #define VSC9953_AC_SMAC_ENA 0x00000020 162 #define VSC9953_AC_IP6_LBL_ENA 0x00000010 163 #define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008 164 #define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004 165 #define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002 166 #define VSC9953_AC_MASK 0x000000fe 167 168 /* Macros for vsc9953_ana_pgid.port_grp_id[] registers */ 169 #define VSC9953_PGID_PORT_MASK 0x000003ff 170 171 #define VSC9953_MAX_PORTS 10 172 #define VSC9953_PORT_CHECK(port) \ 173 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) 174 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \ 175 ( \ 176 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ 177 ) ? 0 : 1 \ 178 ) 179 #define VSC9953_MAX_VLAN 4096 180 #define VSC9953_VLAN_CHECK(vid) \ 181 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) 182 #define VSC9953_DEFAULT_AGE_TIME 300 183 184 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" 185 186 #define MIIMIND_OPR_PEND 0x00000004 187 188 #define VSC9953_BITMASK(offset) ((BIT(offset)) - 1) 189 #define VSC9953_ENC_BITFIELD(target, offset, width) \ 190 (((target) & VSC9953_BITMASK(width)) << (offset)) 191 192 #define VSC9953_IO_ADDR(target, offset) ((target) + (offset << 2)) 193 194 #define VSC9953_IO_REG(target, offset) (VSC9953_IO_ADDR(target, offset)) 195 #define VSC9953_VCAP_CACHE_ENTRY_DAT(target, ri) \ 196 VSC9953_IO_REG(target, (0x2 + (ri))) 197 198 #define VSC9953_VCAP_CACHE_MASK_DAT(target, ri) \ 199 VSC9953_IO_REG(target, (0x42 + (ri))) 200 201 #define VSC9953_VCAP_CACHE_TG_DAT(target) VSC9953_IO_REG(target, 0xe2) 202 #define VSC9953_VCAP_CFG_MV_CFG(target) VSC9953_IO_REG(target, 0x1) 203 #define VSC9953_VCAP_CFG_MV_CFG_SIZE(target) \ 204 VSC9953_ENC_BITFIELD(target, 0, 16) 205 206 #define VSC9953_VCAP_CFG_UPDATE_CTRL(target) VSC9953_IO_REG(target, 0x0) 207 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(target) \ 208 VSC9953_ENC_BITFIELD(target, 22, 3) 209 210 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(target) \ 211 VSC9953_ENC_BITFIELD(target, 3, 16) 212 213 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2) 214 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) 215 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) 216 #define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) 217 #define VSC9953_VCAP_CACHE_ACTION_DAT(target, ri) \ 218 VSC9953_IO_REG(target, (0x82 + (ri))) 219 220 #define VSC9953_VCAP_CACHE_CNT_DAT(target, ri) \ 221 VSC9953_IO_REG(target, (0xc2 + (ri))) 222 223 #define VSC9953_PORT_OFFSET 1 224 #define VSC9953_IS1_CNT 256 225 #define VSC9953_IS2_CNT 1024 226 #define VSC9953_ES0_CNT 1024 227 228 #define BITS_TO_DWORD(in) (1 + (((in) - 1) / 32)) 229 #define ENTRY_WORDS_ES0 BITS_TO_DWORD(29) 230 #define ENTRY_WORDS_IS1 BITS_TO_DWORD(376) 231 #define ENTRY_WORDS_IS2 BITS_TO_DWORD(376) 232 #define ES0_ACT_WIDTH BITS_TO_DWORD(91) 233 #define ES0_CNT_WIDTH BITS_TO_DWORD(1) 234 #define IS1_ACT_WIDTH BITS_TO_DWORD(320) 235 #define IS1_CNT_WIDTH BITS_TO_DWORD(4) 236 #define IS2_ACT_WIDTH BITS_TO_DWORD(103 - 2 * VSC9953_PORT_OFFSET) 237 #define IS2_CNT_WIDTH BITS_TO_DWORD(4 * 32) 238 #define ES0_ACT_COUNT (VSC9953_ES0_CNT + VSC9953_MAX_PORTS) 239 #define IS1_ACT_COUNT (VSC9953_IS1_CNT + 1) 240 #define IS2_ACT_COUNT (VSC9953_IS2_CNT + VSC9953_MAX_PORTS + 2) 241 242 /* TCAM entries */ 243 enum tcam_sel { 244 TCAM_SEL_ENTRY = BIT(0), 245 TCAM_SEL_ACTION = BIT(1), 246 TCAM_SEL_COUNTER = BIT(2), 247 TCAM_SEL_ALL = VSC9953_BITMASK(3), 248 }; 249 250 enum tcam_cmd { 251 TCAM_CMD_WRITE = 0, 252 TCAM_CMD_READ = 1, 253 TCAM_CMD_MOVE_UP = 2, 254 TCAM_CMD_MOVE_DOWN = 3, 255 TCAM_CMD_INITIALIZE = 4, 256 }; 257 258 struct vsc9953_mdio_info { 259 struct vsc9953_mii_mng *regs; 260 char *name; 261 }; 262 263 /* VSC9953 ANA structure */ 264 265 struct vsc9953_ana_port { 266 u32 vlan_cfg; 267 u32 drop_cfg; 268 u32 qos_cfg; 269 u32 vcap_cfg; 270 u32 vcap_s1_key_cfg[3]; 271 u32 vcap_s2_cfg; 272 u32 qos_pcp_dei_map_cfg[16]; 273 u32 cpu_fwd_cfg; 274 u32 cpu_fwd_bpdu_cfg; 275 u32 cpu_fwd_garp_cfg; 276 u32 cpu_fwd_ccm_cfg; 277 u32 port_cfg; 278 u32 pol_cfg; 279 u32 reserved[34]; 280 }; 281 282 struct vsc9953_ana_pol { 283 u32 pol_pir_cfg; 284 u32 pol_cir_cfg; 285 u32 pol_mode_cfg; 286 u32 pol_pir_state; 287 u32 pol_cir_state; 288 u32 reserved1[3]; 289 }; 290 291 struct vsc9953_ana_ana_tables { 292 u32 entry_lim[11]; 293 u32 an_moved; 294 u32 mach_data; 295 u32 macl_data; 296 u32 mac_access; 297 u32 mact_indx; 298 u32 vlan_access; 299 u32 vlan_tidx; 300 }; 301 302 struct vsc9953_ana_ana { 303 u32 adv_learn; 304 u32 vlan_mask; 305 u32 reserved; 306 u32 anag_efil; 307 u32 an_events; 308 u32 storm_limit_burst; 309 u32 storm_limit_cfg[4]; 310 u32 isolated_prts; 311 u32 community_ports; 312 u32 auto_age; 313 u32 mac_options; 314 u32 learn_disc; 315 u32 agen_ctrl; 316 u32 mirror_ports; 317 u32 emirror_ports; 318 u32 flooding; 319 u32 flooding_ipmc; 320 u32 sflow_cfg[11]; 321 u32 port_mode[12]; 322 }; 323 324 #define PGID_DST_START 0 325 #define PGID_AGGR_START 64 326 #define PGID_SRC_START 80 327 328 struct vsc9953_ana_pgid { 329 u32 port_grp_id[91]; 330 }; 331 332 struct vsc9953_ana_pfc { 333 u32 pfc_cfg; 334 u32 reserved1[15]; 335 }; 336 337 struct vsc9953_ana_pol_misc { 338 u32 pol_flowc[10]; 339 u32 reserved1[17]; 340 u32 pol_hyst; 341 }; 342 343 struct vsc9953_ana_common { 344 u32 aggr_cfg; 345 u32 cpuq_cfg; 346 u32 cpuq_8021_cfg; 347 u32 dscp_cfg; 348 u32 dscp_rewr_cfg; 349 u32 vcap_rng_type_cfg; 350 u32 vcap_rng_val_cfg; 351 u32 discard_cfg; 352 u32 fid_cfg; 353 }; 354 355 struct vsc9953_analyzer { 356 struct vsc9953_ana_port port[11]; 357 u32 reserved1[9536]; 358 struct vsc9953_ana_pol pol[164]; 359 struct vsc9953_ana_ana_tables ana_tables; 360 u32 reserved2[14]; 361 struct vsc9953_ana_ana ana; 362 u32 reserved3[21]; 363 struct vsc9953_ana_pgid port_id_tbl; 364 u32 reserved4[549]; 365 struct vsc9953_ana_pfc pfc[10]; 366 struct vsc9953_ana_pol_misc pol_misc; 367 u32 reserved5[196]; 368 struct vsc9953_ana_common common; 369 }; 370 /* END VSC9953 ANA structure t*/ 371 372 /* VSC9953 DEV_GMII structure */ 373 374 struct vsc9953_dev_gmii_port_mode { 375 u32 clock_cfg; 376 u32 port_misc; 377 u32 reserved1; 378 u32 eee_cfg; 379 }; 380 381 struct vsc9953_dev_gmii_mac_cfg_status { 382 u32 mac_ena_cfg; 383 u32 mac_mode_cfg; 384 u32 mac_maxlen_cfg; 385 u32 mac_tags_cfg; 386 u32 mac_adv_chk_cfg; 387 u32 mac_ifg_cfg; 388 u32 mac_hdx_cfg; 389 u32 mac_fc_mac_low_cfg; 390 u32 mac_fc_mac_high_cfg; 391 u32 mac_sticky; 392 }; 393 394 struct vsc9953_dev_gmii { 395 struct vsc9953_dev_gmii_port_mode port_mode; 396 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; 397 }; 398 399 /* END VSC9953 DEV_GMII structure */ 400 401 /* VSC9953 QSYS structure */ 402 403 struct vsc9953_qsys_hsch { 404 u32 cir_cfg; 405 u32 reserved1; 406 u32 se_cfg; 407 u32 se_dwrr_cfg[8]; 408 u32 cir_state; 409 u32 reserved2[20]; 410 }; 411 412 struct vsc9953_qsys_sys { 413 u32 port_mode[12]; 414 u32 switch_port_mode[11]; 415 u32 stat_cnt_cfg; 416 u32 eee_cfg[10]; 417 u32 eee_thrs; 418 u32 igr_no_sharing; 419 u32 egr_no_sharing; 420 u32 sw_status[11]; 421 u32 ext_cpu_cfg; 422 u32 cpu_group_map; 423 u32 reserved1[23]; 424 }; 425 426 struct vsc9953_qsys_qos_cfg { 427 u32 red_profile[16]; 428 u32 res_qos_mode; 429 }; 430 431 struct vsc9953_qsys_drop_cfg { 432 u32 egr_drop_mode; 433 }; 434 435 struct vsc9953_qsys_mmgt { 436 u32 eq_cntrl; 437 u32 reserved1; 438 }; 439 440 struct vsc9953_qsys_hsch_misc { 441 u32 hsch_misc_cfg; 442 u32 reserved1[546]; 443 }; 444 445 struct vsc9953_qsys_res_ctrl { 446 u32 res_cfg; 447 u32 res_stat; 448 449 }; 450 451 struct vsc9953_qsys_reg { 452 struct vsc9953_qsys_hsch hsch[108]; 453 struct vsc9953_qsys_sys sys; 454 struct vsc9953_qsys_qos_cfg qos_cfg; 455 struct vsc9953_qsys_drop_cfg drop_cfg; 456 struct vsc9953_qsys_mmgt mmgt; 457 struct vsc9953_qsys_hsch_misc hsch_misc; 458 struct vsc9953_qsys_res_ctrl res_ctrl[1024]; 459 }; 460 461 /* END VSC9953 QSYS structure */ 462 463 /* VSC9953 SYS structure */ 464 465 struct vsc9953_rx_cntrs { 466 u32 c_rx_oct; 467 u32 c_rx_uc; 468 u32 c_rx_mc; 469 u32 c_rx_bc; 470 u32 c_rx_short; 471 u32 c_rx_frag; 472 u32 c_rx_jabber; 473 u32 c_rx_crc; 474 u32 c_rx_symbol_err; 475 u32 c_rx_sz_64; 476 u32 c_rx_sz_65_127; 477 u32 c_rx_sz_128_255; 478 u32 c_rx_sz_256_511; 479 u32 c_rx_sz_512_1023; 480 u32 c_rx_sz_1024_1526; 481 u32 c_rx_sz_jumbo; 482 u32 c_rx_pause; 483 u32 c_rx_control; 484 u32 c_rx_long; 485 u32 c_rx_cat_drop; 486 u32 c_rx_red_prio_0; 487 u32 c_rx_red_prio_1; 488 u32 c_rx_red_prio_2; 489 u32 c_rx_red_prio_3; 490 u32 c_rx_red_prio_4; 491 u32 c_rx_red_prio_5; 492 u32 c_rx_red_prio_6; 493 u32 c_rx_red_prio_7; 494 u32 c_rx_yellow_prio_0; 495 u32 c_rx_yellow_prio_1; 496 u32 c_rx_yellow_prio_2; 497 u32 c_rx_yellow_prio_3; 498 u32 c_rx_yellow_prio_4; 499 u32 c_rx_yellow_prio_5; 500 u32 c_rx_yellow_prio_6; 501 u32 c_rx_yellow_prio_7; 502 u32 c_rx_green_prio_0; 503 u32 c_rx_green_prio_1; 504 u32 c_rx_green_prio_2; 505 u32 c_rx_green_prio_3; 506 u32 c_rx_green_prio_4; 507 u32 c_rx_green_prio_5; 508 u32 c_rx_green_prio_6; 509 u32 c_rx_green_prio_7; 510 u32 reserved[20]; 511 }; 512 513 struct vsc9953_tx_cntrs { 514 u32 c_tx_oct; 515 u32 c_tx_uc; 516 u32 c_tx_mc; 517 u32 c_tx_bc; 518 u32 c_tx_col; 519 u32 c_tx_drop; 520 u32 c_tx_pause; 521 u32 c_tx_sz_64; 522 u32 c_tx_sz_65_127; 523 u32 c_tx_sz_128_255; 524 u32 c_tx_sz_256_511; 525 u32 c_tx_sz_512_1023; 526 u32 c_tx_sz_1024_1526; 527 u32 c_tx_sz_jumbo; 528 u32 c_tx_yellow_prio_0; 529 u32 c_tx_yellow_prio_1; 530 u32 c_tx_yellow_prio_2; 531 u32 c_tx_yellow_prio_3; 532 u32 c_tx_yellow_prio_4; 533 u32 c_tx_yellow_prio_5; 534 u32 c_tx_yellow_prio_6; 535 u32 c_tx_yellow_prio_7; 536 u32 c_tx_green_prio_0; 537 u32 c_tx_green_prio_1; 538 u32 c_tx_green_prio_2; 539 u32 c_tx_green_prio_3; 540 u32 c_tx_green_prio_4; 541 u32 c_tx_green_prio_5; 542 u32 c_tx_green_prio_6; 543 u32 c_tx_green_prio_7; 544 u32 c_tx_aged; 545 u32 reserved[33]; 546 }; 547 548 struct vsc9953_drop_cntrs { 549 u32 c_dr_local; 550 u32 c_dr_tail; 551 u32 c_dr_yellow_prio_0; 552 u32 c_dr_yellow_prio_1; 553 u32 c_dr_yellow_prio_2; 554 u32 c_dr_yellow_prio_3; 555 u32 c_dr_yellow_prio_4; 556 u32 c_dr_yellow_prio_5; 557 u32 c_dr_yellow_prio_6; 558 u32 c_dr_yellow_prio_7; 559 u32 c_dr_green_prio_0; 560 u32 c_dr_green_prio_1; 561 u32 c_dr_green_prio_2; 562 u32 c_dr_green_prio_3; 563 u32 c_dr_green_prio_4; 564 u32 c_dr_green_prio_5; 565 u32 c_dr_green_prio_6; 566 u32 c_dr_green_prio_7; 567 u32 reserved[46]; 568 }; 569 570 struct vsc9953_sys_stat { 571 struct vsc9953_rx_cntrs rx_cntrs; 572 struct vsc9953_tx_cntrs tx_cntrs; 573 struct vsc9953_drop_cntrs drop_cntrs; 574 u32 reserved1[6]; 575 }; 576 577 struct vsc9953_sys_sys { 578 u32 reset_cfg; 579 u32 reserved1; 580 u32 vlan_etype_cfg; 581 u32 port_mode[12]; 582 u32 front_port_mode[10]; 583 u32 frame_aging; 584 u32 stat_cfg; 585 u32 reserved2[50]; 586 }; 587 588 struct vsc9953_sys_pause_cfg { 589 u32 pause_cfg[11]; 590 u32 pause_tot_cfg; 591 u32 tail_drop_level[11]; 592 u32 tot_tail_drop_lvl; 593 u32 mac_fc_cfg[10]; 594 }; 595 596 struct vsc9953_sys_mmgt { 597 u16 free_cnt; 598 }; 599 600 struct vsc9953_system_reg { 601 struct vsc9953_sys_stat stat; 602 struct vsc9953_sys_sys sys; 603 struct vsc9953_sys_pause_cfg pause_cfg; 604 struct vsc9953_sys_mmgt mmgt; 605 }; 606 607 /* END VSC9953 SYS structure */ 608 609 /* VSC9953 REW structure */ 610 611 struct vsc9953_rew_port { 612 u32 port_vlan_cfg; 613 u32 port_tag_cfg; 614 u32 port_port_cfg; 615 u32 port_dscp_cfg; 616 u32 port_pcp_dei_qos_map_cfg[16]; 617 u32 reserved[12]; 618 }; 619 620 struct vsc9953_rew_common { 621 u32 reserve[4]; 622 u32 dscp_remap_dp1_cfg[64]; 623 u32 dscp_remap_cfg[64]; 624 }; 625 626 struct vsc9953_rew_reg { 627 struct vsc9953_rew_port port[12]; 628 struct vsc9953_rew_common common; 629 }; 630 631 /* END VSC9953 REW structure */ 632 633 /* VSC9953 DEVCPU_GCB structure */ 634 635 struct vsc9953_chip_regs { 636 u32 chipd_id; 637 u32 gpr; 638 u32 soft_rst; 639 }; 640 641 struct vsc9953_gpio { 642 u32 gpio_out_set[10]; 643 u32 gpio_out_clr[10]; 644 u32 gpio_out[10]; 645 u32 gpio_in[10]; 646 }; 647 648 struct vsc9953_mii_mng { 649 u32 miimstatus; 650 u32 reserved1; 651 u32 miimcmd; 652 u32 miimdata; 653 u32 miimcfg; 654 u32 miimscan_0; 655 u32 miimscan_1; 656 u32 miiscan_lst_rslts; 657 u32 miiscan_lst_rslts_valid; 658 }; 659 660 struct vsc9953_mii_read_scan { 661 u32 mii_scan_results_sticky[2]; 662 }; 663 664 struct vsc9953_devcpu_gcb { 665 struct vsc9953_chip_regs chip_regs; 666 struct vsc9953_gpio gpio; 667 struct vsc9953_mii_mng mii_mng[2]; 668 struct vsc9953_mii_read_scan mii_read_scan; 669 }; 670 671 /* END VSC9953 DEVCPU_GCB structure */ 672 673 /* VSC9953 IS* structure */ 674 675 struct vsc9953_vcap_core_cfg { 676 u32 vcap_update_ctrl; 677 u32 vcap_mv_cfg; 678 }; 679 680 struct vsc9953_vcap { 681 struct vsc9953_vcap_core_cfg vcap_core_cfg; 682 }; 683 684 /* END VSC9953 IS* structure */ 685 686 #define VSC9953_PORT_INFO_INITIALIZER(idx) \ 687 { \ 688 .enabled = 0, \ 689 .phyaddr = 0, \ 690 .index = idx, \ 691 .phy_regs = NULL, \ 692 .enet_if = PHY_INTERFACE_MODE_NA, \ 693 .bus = NULL, \ 694 .phydev = NULL, \ 695 } 696 697 /* Structure to describe a VSC9953 port */ 698 struct vsc9953_port_info { 699 u8 enabled; 700 u8 phyaddr; 701 int index; 702 void *phy_regs; 703 phy_interface_t enet_if; 704 struct mii_dev *bus; 705 struct phy_device *phydev; 706 }; 707 708 /* Structure to describe a VSC9953 switch */ 709 struct vsc9953_info { 710 struct vsc9953_port_info port[VSC9953_MAX_PORTS]; 711 }; 712 713 void vsc9953_init(struct bd_info *bis); 714 715 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); 716 void vsc9953_port_info_set_phy_address(int port_no, int address); 717 void vsc9953_port_enable(int port_no); 718 void vsc9953_port_disable(int port_no); 719 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); 720 721 #endif /* _VSC9953_H_ */ 722