1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2012-2013, Xilinx, Michal Simek
4  *
5  * (C) Copyright 2012
6  * Joe Hershberger <joe.hershberger@ni.com>
7  */
8 
9 #ifndef _ZYNQPL_H_
10 #define _ZYNQPL_H_
11 
12 #include <xilinx.h>
13 
14 #ifdef CONFIG_CMD_ZYNQ_AES
15 int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen,
16 		      u8 bstype);
17 #endif
18 
19 extern struct xilinx_fpga_op zynq_op;
20 
21 #define XILINX_ZYNQ_XC7Z007S	0x3
22 #define XILINX_ZYNQ_XC7Z010	0x2
23 #define XILINX_ZYNQ_XC7Z010_LR	0x4
24 #define XILINX_ZYNQ_XC7Z012S	0x1c
25 #define XILINX_ZYNQ_XC7Z014S	0x8
26 #define XILINX_ZYNQ_XC7Z015	0x1b
27 #define XILINX_ZYNQ_XC7Z020_LR	0x9
28 #define XILINX_ZYNQ_XC7Z020	0x7
29 #define XILINX_ZYNQ_XC7Z030	0xc
30 #define XILINX_ZYNQ_XC7Z035	0x12
31 #define XILINX_ZYNQ_XC7Z045	0x11
32 #define XILINX_ZYNQ_XC7Z100	0x16
33 
34 /* Device Image Sizes */
35 #define XILINX_XC7Z007S_SIZE	16669920/8
36 #define XILINX_XC7Z010_SIZE	16669920/8
37 #define XILINX_XC7Z010_LR_SIZE	16669920/8
38 #define XILINX_XC7Z012S_SIZE	28085344/8
39 #define XILINX_XC7Z014S_SIZE	32364512/8
40 #define XILINX_XC7Z015_SIZE	28085344/8
41 #define XILINX_XC7Z020_LR_SIZE	32364512/8
42 #define XILINX_XC7Z020_SIZE	32364512/8
43 #define XILINX_XC7Z030_SIZE	47839328/8
44 #define XILINX_XC7Z035_SIZE	106571232/8
45 #define XILINX_XC7Z045_SIZE	106571232/8
46 #define XILINX_XC7Z100_SIZE	139330784/8
47 
48 /* Device Names */
49 #define XILINX_XC7Z007S_NAME	"7z007s"
50 #define XILINX_XC7Z010_NAME	"7z010"
51 #define XILINX_XC7Z010_LR_NAME	"xc7z010_lr"
52 #define XILINX_XC7Z012S_NAME	"7z012s"
53 #define XILINX_XC7Z014S_NAME	"7z014s"
54 #define XILINX_XC7Z015_NAME	"7z015"
55 #define XILINX_XC7Z020_LR_NAME	"xa7z020_lr"
56 #define XILINX_XC7Z020_NAME	"7z020"
57 #define XILINX_XC7Z030_NAME	"7z030"
58 #define XILINX_XC7Z035_NAME	"7z035"
59 #define XILINX_XC7Z045_NAME	"7z045"
60 #define XILINX_XC7Z100_NAME	"7z100"
61 
62 #if defined(CONFIG_FPGA)
63 #define ZYNQ_DESC(name) { \
64 	.idcode = XILINX_ZYNQ_XC##name, \
65 	.fpga_size = XILINX_XC##name##_SIZE, \
66 	.devicename = XILINX_XC##name##_NAME \
67 	}
68 #else
69 #define ZYNQ_DESC(name) { \
70 	.idcode = XILINX_ZYNQ_XC##name, \
71 	.devicename = XILINX_XC##name##_NAME \
72 	}
73 #endif
74 
75 #endif /* _ZYNQPL_H_ */
76