1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 #include <config.h>
8 #include <log.h>
9 #include <asm/global_data.h>
10
11 /* Memory test
12 *
13 * General observations:
14 * o The recommended test sequence is to test the data lines: if they are
15 * broken, nothing else will work properly. Then test the address
16 * lines. Finally, test the cells in the memory now that the test
17 * program knows that the address and data lines work properly.
18 * This sequence also helps isolate and identify what is faulty.
19 *
20 * o For the address line test, it is a good idea to use the base
21 * address of the lowest memory location, which causes a '1' bit to
22 * walk through a field of zeros on the address lines and the highest
23 * memory location, which causes a '0' bit to walk through a field of
24 * '1's on the address line.
25 *
26 * o Floating buses can fool memory tests if the test routine writes
27 * a value and then reads it back immediately. The problem is, the
28 * write will charge the residual capacitance on the data bus so the
29 * bus retains its state briefely. When the test program reads the
30 * value back immediately, the capacitance of the bus can allow it
31 * to read back what was written, even though the memory circuitry
32 * is broken. To avoid this, the test program should write a test
33 * pattern to the target location, write a different pattern elsewhere
34 * to charge the residual capacitance in a differnt manner, then read
35 * the target location back.
36 *
37 * o Always read the target location EXACTLY ONCE and save it in a local
38 * variable. The problem with reading the target location more than
39 * once is that the second and subsequent reads may work properly,
40 * resulting in a failed test that tells the poor technician that
41 * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
42 * doesn't help him one bit and causes puzzled phone calls. Been there,
43 * done that.
44 *
45 * Data line test:
46 * ---------------
47 * This tests data lines for shorts and opens by forcing adjacent data
48 * to opposite states. Because the data lines could be routed in an
49 * arbitrary manner the must ensure test patterns ensure that every case
50 * is tested. By using the following series of binary patterns every
51 * combination of adjacent bits is test regardless of routing.
52 *
53 * ...101010101010101010101010
54 * ...110011001100110011001100
55 * ...111100001111000011110000
56 * ...111111110000000011111111
57 *
58 * Carrying this out, gives us six hex patterns as follows:
59 *
60 * 0xaaaaaaaaaaaaaaaa
61 * 0xcccccccccccccccc
62 * 0xf0f0f0f0f0f0f0f0
63 * 0xff00ff00ff00ff00
64 * 0xffff0000ffff0000
65 * 0xffffffff00000000
66 *
67 * To test for short and opens to other signals on our boards, we
68 * simply test with the 1's complemnt of the paterns as well, resulting
69 * in twelve patterns total.
70 *
71 * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
72 * written to a different address in case the data lines are floating.
73 * Thus, if a byte lane fails, you will see part of the special
74 * pattern in that byte lane when the test runs. For example, if the
75 * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
76 * (for the 'a' test pattern).
77 *
78 * Address line test:
79 * ------------------
80 * This function performs a test to verify that all the address lines
81 * hooked up to the RAM work properly. If there is an address line
82 * fault, it usually shows up as two different locations in the address
83 * map (related by the faulty address line) mapping to one physical
84 * memory storage location. The artifact that shows up is writing to
85 * the first location "changes" the second location.
86 *
87 * To test all address lines, we start with the given base address and
88 * xor the address with a '1' bit to flip one address line. For each
89 * test, we shift the '1' bit left to test the next address line.
90 *
91 * In the actual code, we start with address sizeof(ulong) since our
92 * test pattern we use is a ulong and thus, if we tried to test lower
93 * order address bits, it wouldn't work because our pattern would
94 * overwrite itself.
95 *
96 * Example for a 4 bit address space with the base at 0000:
97 * 0000 <- base
98 * 0001 <- test 1
99 * 0010 <- test 2
100 * 0100 <- test 3
101 * 1000 <- test 4
102 * Example for a 4 bit address space with the base at 0010:
103 * 0010 <- base
104 * 0011 <- test 1
105 * 0000 <- (below the base address, skipped)
106 * 0110 <- test 2
107 * 1010 <- test 3
108 *
109 * The test locations are successively tested to make sure that they are
110 * not "mirrored" onto the base address due to a faulty address line.
111 * Note that the base and each test location are related by one address
112 * line flipped. Note that the base address need not be all zeros.
113 *
114 * Memory tests 1-4:
115 * -----------------
116 * These tests verify RAM using sequential writes and reads
117 * to/from RAM. There are several test cases that use different patterns to
118 * verify RAM. Each test case fills a region of RAM with one pattern and
119 * then reads the region back and compares its contents with the pattern.
120 * The following patterns are used:
121 *
122 * 1a) zero pattern (0x00000000)
123 * 1b) negative pattern (0xffffffff)
124 * 1c) checkerboard pattern (0x55555555)
125 * 1d) checkerboard pattern (0xaaaaaaaa)
126 * 2) bit-flip pattern ((1 << (offset % 32))
127 * 3) address pattern (offset)
128 * 4) address pattern (~offset)
129 *
130 * Being run in normal mode, the test verifies only small 4Kb
131 * regions of RAM around each 1Mb boundary. For example, for 64Mb
132 * RAM the following areas are verified: 0x00000000-0x00000800,
133 * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
134 * 0x04000000. If the test is run in slow-test mode, it verifies
135 * the whole RAM.
136 */
137
138 #include <post.h>
139 #include <watchdog.h>
140
141 #if CFG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS)
142
143 DECLARE_GLOBAL_DATA_PTR;
144
145 /*
146 * Define INJECT_*_ERRORS for testing error detection in the presence of
147 * _good_ hardware.
148 */
149 #undef INJECT_DATA_ERRORS
150 #undef INJECT_ADDRESS_ERRORS
151
152 #ifdef INJECT_DATA_ERRORS
153 #warning "Injecting data line errors for testing purposes"
154 #endif
155
156 #ifdef INJECT_ADDRESS_ERRORS
157 #warning "Injecting address line errors for testing purposes"
158 #endif
159
160 /*
161 * This function performs a double word move from the data at
162 * the source pointer to the location at the destination pointer.
163 * This is helpful for testing memory on processors which have a 64 bit
164 * wide data bus.
165 *
166 * On those PowerPC with FPU, use assembly and a floating point move:
167 * this does a 64 bit move.
168 *
169 * For other processors, let the compiler generate the best code it can.
170 */
move64(const unsigned long long * src,unsigned long long * dest)171 static void move64(const unsigned long long *src, unsigned long long *dest)
172 {
173 *dest = *src;
174 }
175
176 /*
177 * This is 64 bit wide test patterns. Note that they reside in ROM
178 * (which presumably works) and the tests write them to RAM which may
179 * not work.
180 *
181 * The "otherpattern" is written to drive the data bus to values other
182 * than the test pattern. This is for detecting floating bus lines.
183 *
184 */
185 const static unsigned long long pattern[] = {
186 0xaaaaaaaaaaaaaaaaULL,
187 0xccccccccccccccccULL,
188 0xf0f0f0f0f0f0f0f0ULL,
189 0xff00ff00ff00ff00ULL,
190 0xffff0000ffff0000ULL,
191 0xffffffff00000000ULL,
192 0x00000000ffffffffULL,
193 0x0000ffff0000ffffULL,
194 0x00ff00ff00ff00ffULL,
195 0x0f0f0f0f0f0f0f0fULL,
196 0x3333333333333333ULL,
197 0x5555555555555555ULL
198 };
199 const unsigned long long otherpattern = 0x0123456789abcdefULL;
200
memory_post_dataline(unsigned long long * pmem)201 static int memory_post_dataline(unsigned long long * pmem)
202 {
203 unsigned long long temp64 = 0;
204 int num_patterns = ARRAY_SIZE(pattern);
205 int i;
206 unsigned int hi, lo, pathi, patlo;
207 int ret = 0;
208
209 for ( i = 0; i < num_patterns; i++) {
210 move64(&(pattern[i]), pmem++);
211 /*
212 * Put a different pattern on the data lines: otherwise they
213 * may float long enough to read back what we wrote.
214 */
215 move64(&otherpattern, pmem--);
216 move64(pmem, &temp64);
217
218 #ifdef INJECT_DATA_ERRORS
219 temp64 ^= 0x00008000;
220 #endif
221
222 if (temp64 != pattern[i]){
223 pathi = (pattern[i]>>32) & 0xffffffff;
224 patlo = pattern[i] & 0xffffffff;
225
226 hi = (temp64>>32) & 0xffffffff;
227 lo = temp64 & 0xffffffff;
228
229 post_log("Memory (data line) error at %p, wrote %08x%08x, read %08x%08x !\n",
230 pmem, pathi, patlo, hi, lo);
231 ret = -1;
232 }
233 }
234 return ret;
235 }
236
memory_post_addrline(ulong * testaddr,ulong * base,ulong size)237 static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
238 {
239 ulong *target;
240 ulong *end;
241 ulong readback;
242 ulong xor;
243 int ret = 0;
244
245 end = (ulong *)((ulong)base + size); /* pointer arith! */
246 xor = 0;
247 for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
248 target = (ulong *)((ulong)testaddr ^ xor);
249 if((target >= base) && (target < end)) {
250 *testaddr = ~*target;
251 readback = *target;
252
253 #ifdef INJECT_ADDRESS_ERRORS
254 if(xor == 0x00008000) {
255 readback = *testaddr;
256 }
257 #endif
258 if(readback == *testaddr) {
259 post_log("Memory (address line) error at %p<->%p, XOR value %08lx !\n",
260 testaddr, target, xor);
261 ret = -1;
262 }
263 }
264 }
265 return ret;
266 }
267
memory_post_test1(unsigned long start,unsigned long size,unsigned long val)268 static int memory_post_test1(unsigned long start,
269 unsigned long size,
270 unsigned long val)
271 {
272 unsigned long i;
273 ulong *mem = (ulong *) start;
274 ulong readback;
275 int ret = 0;
276
277 for (i = 0; i < size / sizeof (ulong); i++) {
278 mem[i] = val;
279 if (i % 1024 == 0)
280 schedule();
281 }
282
283 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
284 readback = mem[i];
285 if (readback != val) {
286 post_log("Memory error at %p, wrote %08lx, read %08lx !\n",
287 mem + i, val, readback);
288
289 ret = -1;
290 break;
291 }
292 if (i % 1024 == 0)
293 schedule();
294 }
295
296 return ret;
297 }
298
memory_post_test2(unsigned long start,unsigned long size)299 static int memory_post_test2(unsigned long start, unsigned long size)
300 {
301 unsigned long i;
302 ulong *mem = (ulong *) start;
303 ulong readback;
304 int ret = 0;
305
306 for (i = 0; i < size / sizeof (ulong); i++) {
307 mem[i] = 1 << (i % 32);
308 if (i % 1024 == 0)
309 schedule();
310 }
311
312 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
313 readback = mem[i];
314 if (readback != (1 << (i % 32))) {
315 post_log("Memory error at %p, wrote %08lx, read %08lx !\n",
316 mem + i, 1UL << (i % 32), readback);
317
318 ret = -1;
319 break;
320 }
321 if (i % 1024 == 0)
322 schedule();
323 }
324
325 return ret;
326 }
327
memory_post_test3(unsigned long start,unsigned long size)328 static int memory_post_test3(unsigned long start, unsigned long size)
329 {
330 unsigned long i;
331 ulong *mem = (ulong *) start;
332 ulong readback;
333 int ret = 0;
334
335 for (i = 0; i < size / sizeof (ulong); i++) {
336 mem[i] = i;
337 if (i % 1024 == 0)
338 schedule();
339 }
340
341 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
342 readback = mem[i];
343 if (readback != i) {
344 post_log("Memory error at %p, wrote %08lx, read %08lx !\n",
345 mem + i, i, readback);
346
347 ret = -1;
348 break;
349 }
350 if (i % 1024 == 0)
351 schedule();
352 }
353
354 return ret;
355 }
356
memory_post_test4(unsigned long start,unsigned long size)357 static int memory_post_test4(unsigned long start, unsigned long size)
358 {
359 unsigned long i;
360 ulong *mem = (ulong *) start;
361 ulong readback;
362 int ret = 0;
363
364 for (i = 0; i < size / sizeof (ulong); i++) {
365 mem[i] = ~i;
366 if (i % 1024 == 0)
367 schedule();
368 }
369
370 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
371 readback = mem[i];
372 if (readback != ~i) {
373 post_log("Memory error at %p, wrote %08lx, read %08lx !\n",
374 mem + i, ~i, readback);
375
376 ret = -1;
377 break;
378 }
379 if (i % 1024 == 0)
380 schedule();
381 }
382
383 return ret;
384 }
385
memory_post_test_lines(unsigned long start,unsigned long size)386 static int memory_post_test_lines(unsigned long start, unsigned long size)
387 {
388 int ret = 0;
389
390 ret = memory_post_dataline((unsigned long long *)start);
391 schedule();
392 if (!ret)
393 ret = memory_post_addrline((ulong *)start, (ulong *)start,
394 size);
395 schedule();
396 if (!ret)
397 ret = memory_post_addrline((ulong *)(start+size-8),
398 (ulong *)start, size);
399 schedule();
400
401 return ret;
402 }
403
memory_post_test_patterns(unsigned long start,unsigned long size)404 static int memory_post_test_patterns(unsigned long start, unsigned long size)
405 {
406 int ret = 0;
407
408 ret = memory_post_test1(start, size, 0x00000000);
409 schedule();
410 if (!ret)
411 ret = memory_post_test1(start, size, 0xffffffff);
412 schedule();
413 if (!ret)
414 ret = memory_post_test1(start, size, 0x55555555);
415 schedule();
416 if (!ret)
417 ret = memory_post_test1(start, size, 0xaaaaaaaa);
418 schedule();
419 if (!ret)
420 ret = memory_post_test2(start, size);
421 schedule();
422 if (!ret)
423 ret = memory_post_test3(start, size);
424 schedule();
425 if (!ret)
426 ret = memory_post_test4(start, size);
427 schedule();
428
429 return ret;
430 }
431
memory_post_test_regions(unsigned long start,unsigned long size)432 static int memory_post_test_regions(unsigned long start, unsigned long size)
433 {
434 unsigned long i;
435 int ret = 0;
436
437 for (i = 0; i < (size >> 20) && (!ret); i++) {
438 if (!ret)
439 ret = memory_post_test_patterns(start + (i << 20),
440 0x800);
441 if (!ret)
442 ret = memory_post_test_patterns(start + (i << 20) +
443 0xff800, 0x800);
444 }
445
446 return ret;
447 }
448
memory_post_tests(unsigned long start,unsigned long size)449 static int memory_post_tests(unsigned long start, unsigned long size)
450 {
451 int ret = 0;
452
453 ret = memory_post_test_lines(start, size);
454 if (!ret)
455 ret = memory_post_test_patterns(start, size);
456
457 return ret;
458 }
459
460 /*
461 * !! this is only valid, if you have contiguous memory banks !!
462 */
463 __attribute__((weak))
arch_memory_test_prepare(u32 * vstart,u32 * size,phys_addr_t * phys_offset)464 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
465 {
466 struct bd_info *bd = gd->bd;
467
468 *vstart = CFG_SYS_SDRAM_BASE;
469 *size = (gd->ram_size >= 256 << 20 ?
470 256 << 20 : gd->ram_size) - (1 << 20);
471
472 /* Limit area to be tested with the board info struct */
473 if ((*vstart) + (*size) > (ulong)bd)
474 *size = (ulong)bd - *vstart;
475
476 return 0;
477 }
478
479 __attribute__((weak))
arch_memory_test_advance(u32 * vstart,u32 * size,phys_addr_t * phys_offset)480 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
481 {
482 return 1;
483 }
484
485 __attribute__((weak))
arch_memory_test_cleanup(u32 * vstart,u32 * size,phys_addr_t * phys_offset)486 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
487 {
488 return 0;
489 }
490
491 __attribute__((weak))
arch_memory_failure_handle(void)492 void arch_memory_failure_handle(void)
493 {
494 return;
495 }
496
memory_regions_post_test(int flags)497 int memory_regions_post_test(int flags)
498 {
499 int ret = 0;
500 phys_addr_t phys_offset = 0;
501 u32 memsize, vstart;
502
503 arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
504
505 ret = memory_post_test_lines(vstart, memsize);
506 if (!ret)
507 ret = memory_post_test_regions(vstart, memsize);
508
509 return ret;
510 }
511
memory_post_test(int flags)512 int memory_post_test(int flags)
513 {
514 int ret = 0;
515 phys_addr_t phys_offset = 0;
516 u32 memsize, vstart;
517
518 arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
519
520 do {
521 if (flags & POST_SLOWTEST) {
522 ret = memory_post_tests(vstart, memsize);
523 } else { /* POST_NORMAL */
524 ret = memory_post_test_regions(vstart, memsize);
525 }
526 } while (!ret &&
527 !arch_memory_test_advance(&vstart, &memsize, &phys_offset));
528
529 arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
530 if (ret)
531 arch_memory_failure_handle();
532
533 return ret;
534 }
535
536 #endif /* CFG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */
537