1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Google, Inc
4 *
5 * Note: Test coverage does not include 10-bit addressing
6 */
7
8 #include <dm.h>
9 #include <fdtdec.h>
10 #include <i2c.h>
11 #include <asm/state.h>
12 #include <asm/test.h>
13 #include <dm/device-internal.h>
14 #include <dm/test.h>
15 #include <dm/uclass-internal.h>
16 #include <dm/util.h>
17 #include <hexdump.h>
18 #include <test/test.h>
19 #include <test/ut.h>
20
21 static const int busnum;
22 static const int chip = 0x2c;
23
24 /* Test that we can find buses and chips */
dm_test_i2c_find(struct unit_test_state * uts)25 static int dm_test_i2c_find(struct unit_test_state *uts)
26 {
27 struct udevice *bus, *dev;
28 const int no_chip = 0x10;
29
30 /*
31 * The post_bind() method will bind devices to chip selects. Check
32 * this then remove the emulation and the slave device.
33 */
34 ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
35 ut_assertok(dm_i2c_probe(bus, chip, 0, &dev));
36 ut_asserteq(-ENOENT, dm_i2c_probe(bus, no_chip, 0, &dev));
37 ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_I2C, 1, &bus));
38
39 return 0;
40 }
41 DM_TEST(dm_test_i2c_find, UTF_SCAN_PDATA | UTF_SCAN_FDT);
42
dm_test_i2c_read_write(struct unit_test_state * uts)43 static int dm_test_i2c_read_write(struct unit_test_state *uts)
44 {
45 struct udevice *bus, *dev;
46 uint8_t buf[5];
47
48 ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
49 ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
50 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
51 ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
52 ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
53 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
54 ut_asserteq_mem(buf, "\0\0AB\0", sizeof(buf));
55
56 return 0;
57 }
58 DM_TEST(dm_test_i2c_read_write, UTF_SCAN_PDATA | UTF_SCAN_FDT);
59
dm_test_i2c_speed(struct unit_test_state * uts)60 static int dm_test_i2c_speed(struct unit_test_state *uts)
61 {
62 struct udevice *bus, *dev;
63 uint8_t buf[5];
64
65 ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
66
67 /* Use test mode so we create the required errors for invalid speeds */
68 sandbox_i2c_set_test_mode(bus, true);
69 ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
70 ut_assertok(dm_i2c_set_bus_speed(bus, 100000));
71 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
72 ut_assertok(dm_i2c_set_bus_speed(bus, 400000));
73 ut_asserteq(400000, dm_i2c_get_bus_speed(bus));
74 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
75 ut_asserteq(-EINVAL, dm_i2c_write(dev, 0, buf, 5));
76 sandbox_i2c_set_test_mode(bus, false);
77
78 return 0;
79 }
80 DM_TEST(dm_test_i2c_speed, UTF_SCAN_PDATA | UTF_SCAN_FDT);
81
dm_test_i2c_offset_len(struct unit_test_state * uts)82 static int dm_test_i2c_offset_len(struct unit_test_state *uts)
83 {
84 struct udevice *bus, *dev;
85 uint8_t buf[5];
86
87 ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
88 ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
89 ut_assertok(i2c_set_chip_offset_len(dev, 1));
90 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
91
92 /* This is not supported by the uclass */
93 ut_asserteq(-EINVAL, i2c_set_chip_offset_len(dev, 5));
94
95 return 0;
96 }
97 DM_TEST(dm_test_i2c_offset_len, UTF_SCAN_PDATA | UTF_SCAN_FDT);
98
dm_test_i2c_probe_empty(struct unit_test_state * uts)99 static int dm_test_i2c_probe_empty(struct unit_test_state *uts)
100 {
101 struct udevice *bus, *dev;
102
103 ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
104
105 /* Use test mode so that this chip address will always probe */
106 sandbox_i2c_set_test_mode(bus, true);
107 ut_assertok(dm_i2c_probe(bus, SANDBOX_I2C_TEST_ADDR, 0, &dev));
108 sandbox_i2c_set_test_mode(bus, false);
109
110 return 0;
111 }
112 DM_TEST(dm_test_i2c_probe_empty, UTF_SCAN_PDATA | UTF_SCAN_FDT);
113
dm_test_i2c_bytewise(struct unit_test_state * uts)114 static int dm_test_i2c_bytewise(struct unit_test_state *uts)
115 {
116 struct udevice *bus, *dev;
117 struct udevice *eeprom;
118 uint8_t buf[5];
119
120 ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
121 ut_assertok(i2c_get_chip(bus, chip, 1, &dev));
122 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
123 ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
124
125 /* Tell the EEPROM to only read/write one register at a time */
126 ut_assertok(uclass_first_device_err(UCLASS_I2C_EMUL, &eeprom));
127 ut_assertnonnull(eeprom);
128 sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_SINGLE_BYTE);
129
130 /* Now we only get the first byte - the rest will be 0xff */
131 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
132 ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
133
134 /* If we do a separate transaction for each byte, it works */
135 ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
136 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
137 ut_asserteq_mem(buf, "\0\0\0\0\0", sizeof(buf));
138
139 /* This will only write A */
140 ut_assertok(i2c_set_chip_flags(dev, 0));
141 ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
142 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
143 ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
144
145 /* Check that the B was ignored */
146 ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
147 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
148 ut_asserteq_mem(buf, "\0\0A\0\0\0", sizeof(buf));
149
150 /* Now write it again with the new flags, it should work */
151 ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS));
152 ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
153 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
154 ut_asserteq_mem(buf, "\0\xff\xff\xff\xff", sizeof(buf));
155
156 ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS |
157 DM_I2C_CHIP_RD_ADDRESS));
158 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
159 ut_asserteq_mem(buf, "\0\0AB\0\0", sizeof(buf));
160
161 /* Restore defaults */
162 sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_NONE);
163 ut_assertok(i2c_set_chip_flags(dev, 0));
164
165 return 0;
166 }
167 DM_TEST(dm_test_i2c_bytewise, UTF_SCAN_PDATA | UTF_SCAN_FDT);
168
dm_test_i2c_offset(struct unit_test_state * uts)169 static int dm_test_i2c_offset(struct unit_test_state *uts)
170 {
171 struct udevice *eeprom;
172 struct udevice *dev;
173 uint8_t buf[5];
174
175 ut_assertok(i2c_get_chip_for_busnum(busnum, chip, 1, &dev));
176
177 /* Do a transfer so we can find the emulator */
178 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
179 ut_assertok(uclass_first_device_err(UCLASS_I2C_EMUL, &eeprom));
180
181 /* Offset length 0 */
182 sandbox_i2c_eeprom_set_offset_len(eeprom, 0);
183 ut_assertok(i2c_set_chip_offset_len(dev, 0));
184 ut_assertok(dm_i2c_write(dev, 10 /* ignored */, (uint8_t *)"AB", 2));
185 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
186 ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
187 ut_asserteq(0, sanbox_i2c_eeprom_get_prev_offset(eeprom));
188
189 /* Offset length 1 */
190 sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
191 ut_assertok(i2c_set_chip_offset_len(dev, 1));
192 ut_assertok(dm_i2c_write(dev, 2, (uint8_t *)"AB", 2));
193 ut_asserteq(2, sanbox_i2c_eeprom_get_prev_offset(eeprom));
194 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
195 ut_asserteq_mem("ABAB\0", buf, sizeof(buf));
196 ut_asserteq(0, sanbox_i2c_eeprom_get_prev_offset(eeprom));
197
198 /* Offset length 2 boundary - check model wrapping */
199 sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
200 ut_assertok(i2c_set_chip_offset_len(dev, 2));
201 ut_assertok(dm_i2c_write(dev, 0xFF, (uint8_t *)"A", 1));
202 ut_asserteq(0xFF, sanbox_i2c_eeprom_get_prev_offset(eeprom));
203 ut_assertok(dm_i2c_write(dev, 0x100, (uint8_t *)"B", 1));
204 ut_asserteq(0x100, sanbox_i2c_eeprom_get_prev_offset(eeprom));
205 ut_assertok(dm_i2c_write(dev, 0x101, (uint8_t *)"C", 1));
206 ut_asserteq(0x101, sanbox_i2c_eeprom_get_prev_offset(eeprom));
207 ut_assertok(dm_i2c_read(dev, 0xFF, buf, 5));
208 ut_asserteq_mem("ABCAB", buf, sizeof(buf));
209 ut_asserteq(0xFF, sanbox_i2c_eeprom_get_prev_offset(eeprom));
210
211 /* Offset length 2 */
212 sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
213 ut_assertok(i2c_set_chip_offset_len(dev, 2));
214 ut_assertok(dm_i2c_write(dev, 0x2020, (uint8_t *)"AB", 2));
215 ut_assertok(dm_i2c_read(dev, 0x2020, buf, 5));
216 ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf));
217 ut_asserteq(0x2020, sanbox_i2c_eeprom_get_prev_offset(eeprom));
218
219 /* Offset length 3 */
220 sandbox_i2c_eeprom_set_offset_len(eeprom, 3);
221 ut_assertok(i2c_set_chip_offset_len(dev, 3));
222 ut_assertok(dm_i2c_write(dev, 0x303030, (uint8_t *)"AB", 2));
223 ut_assertok(dm_i2c_read(dev, 0x303030, buf, 5));
224 ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf));
225 ut_asserteq(0x303030, sanbox_i2c_eeprom_get_prev_offset(eeprom));
226
227 /* Offset length 4 */
228 sandbox_i2c_eeprom_set_offset_len(eeprom, 4);
229 ut_assertok(i2c_set_chip_offset_len(dev, 4));
230 ut_assertok(dm_i2c_write(dev, 0x40404040, (uint8_t *)"AB", 2));
231 ut_assertok(dm_i2c_read(dev, 0x40404040, buf, 5));
232 ut_asserteq_mem("AB\0\0\0", buf, sizeof(buf));
233 ut_asserteq(0x40404040, sanbox_i2c_eeprom_get_prev_offset(eeprom));
234
235 /* Restore defaults */
236 sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
237
238 return 0;
239 }
240 DM_TEST(dm_test_i2c_offset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
241
dm_test_i2c_addr_offset(struct unit_test_state * uts)242 static int dm_test_i2c_addr_offset(struct unit_test_state *uts)
243 {
244 struct udevice *eeprom;
245 struct udevice *dev;
246 u8 buf[5];
247
248 ut_assertok(i2c_get_chip_for_busnum(busnum, chip, 1, &dev));
249
250 /* Do a transfer so we can find the emulator */
251 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
252 ut_assertok(uclass_first_device_err(UCLASS_I2C_EMUL, &eeprom));
253
254 /* Offset length 0 */
255 sandbox_i2c_eeprom_set_offset_len(eeprom, 0);
256 sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
257 ut_assertok(i2c_set_chip_offset_len(dev, 0));
258 ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
259 ut_assertok(dm_i2c_write(dev, 0x3, (uint8_t *)"AB", 2));
260 ut_assertok(dm_i2c_read(dev, 0x3, buf, 5));
261 ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
262 ut_asserteq(0x3, sanbox_i2c_eeprom_get_prev_offset(eeprom));
263 ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
264
265 /* Offset length 1 */
266 sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
267 sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
268 ut_assertok(i2c_set_chip_offset_len(dev, 1));
269 ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
270 ut_assertok(dm_i2c_write(dev, 0x310, (uint8_t *)"AB", 2));
271 ut_assertok(dm_i2c_read(dev, 0x310, buf, 5));
272 ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
273 ut_asserteq(0x310, sanbox_i2c_eeprom_get_prev_offset(eeprom));
274 ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
275
276 /* Offset length 2 */
277 sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
278 sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
279 ut_assertok(i2c_set_chip_offset_len(dev, 2));
280 ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
281 ut_assertok(dm_i2c_write(dev, 0x32020, (uint8_t *)"AB", 2));
282 ut_assertok(dm_i2c_read(dev, 0x32020, buf, 5));
283 ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
284 ut_asserteq(0x32020, sanbox_i2c_eeprom_get_prev_offset(eeprom));
285 ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
286
287 /* Offset length 3 */
288 sandbox_i2c_eeprom_set_offset_len(eeprom, 3);
289 sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0x3);
290 ut_assertok(i2c_set_chip_offset_len(dev, 3));
291 ut_assertok(i2c_set_chip_addr_offset_mask(dev, 0x3));
292 ut_assertok(dm_i2c_write(dev, 0x3303030, (uint8_t *)"AB", 2));
293 ut_assertok(dm_i2c_read(dev, 0x3303030, buf, 5));
294 ut_asserteq_mem("AB\0\0\0\0", buf, sizeof(buf));
295 ut_asserteq(0x3303030, sanbox_i2c_eeprom_get_prev_offset(eeprom));
296 ut_asserteq(chip | 0x3, sanbox_i2c_eeprom_get_prev_addr(eeprom));
297
298 /* Restore defaults */
299 sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
300 sandbox_i2c_eeprom_set_chip_addr_offset_mask(eeprom, 0);
301
302 return 0;
303 }
304 DM_TEST(dm_test_i2c_addr_offset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
305
dm_test_i2c_reg_clrset(struct unit_test_state * uts)306 static int dm_test_i2c_reg_clrset(struct unit_test_state *uts)
307 {
308 struct udevice *eeprom;
309 struct udevice *dev;
310 u8 buf[5];
311
312 ut_assertok(i2c_get_chip_for_busnum(busnum, chip, 1, &dev));
313
314 /* Do a transfer so we can find the emulator */
315 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
316 ut_assertok(uclass_first_device_err(UCLASS_I2C_EMUL, &eeprom));
317
318 /* Dummy data for the test */
319 ut_assertok(dm_i2c_write(dev, 0, "\xff\x00\xff\x00\x10", 5));
320
321 /* Do some clrset tests */
322 ut_assertok(dm_i2c_reg_clrset(dev, 0, 0xff, 0x10));
323 ut_assertok(dm_i2c_reg_clrset(dev, 1, 0x00, 0x11));
324 ut_assertok(dm_i2c_reg_clrset(dev, 2, 0xed, 0x00));
325 ut_assertok(dm_i2c_reg_clrset(dev, 3, 0xff, 0x13));
326 ut_assertok(dm_i2c_reg_clrset(dev, 4, 0x00, 0x14));
327
328 ut_assertok(dm_i2c_read(dev, 0, buf, 5));
329 ut_asserteq_mem("\x10\x11\x12\x13\x14", buf, sizeof(buf));
330
331 return 0;
332 }
333 DM_TEST(dm_test_i2c_reg_clrset, UTF_SCAN_PDATA | UTF_SCAN_FDT);
334