1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Tests for the driver model pmic API
4 *
5 * Copyright (c) 2015 Samsung Electronics
6 * Przemyslaw Marczak <p.marczak@samsung.com>
7 */
8
9 #include <errno.h>
10 #include <dm.h>
11 #include <fdtdec.h>
12 #include <fsl_pmic.h>
13 #include <malloc.h>
14 #include <dm/device-internal.h>
15 #include <dm/root.h>
16 #include <dm/test.h>
17 #include <dm/uclass-internal.h>
18 #include <dm/util.h>
19 #include <power/pmic.h>
20 #include <power/sandbox_pmic.h>
21 #include <test/test.h>
22 #include <test/ut.h>
23
24 /* Test PMIC get method */
25
power_pmic_get(struct unit_test_state * uts,char * name)26 static inline int power_pmic_get(struct unit_test_state *uts, char *name)
27 {
28 struct udevice *dev;
29
30 ut_assertok(pmic_get(name, &dev));
31 ut_assertnonnull(dev);
32
33 /* Check PMIC's name */
34 ut_asserteq_str(name, dev->name);
35
36 return 0;
37 }
38
39 /* Test PMIC get method */
dm_test_power_pmic_get(struct unit_test_state * uts)40 static int dm_test_power_pmic_get(struct unit_test_state *uts)
41 {
42 power_pmic_get(uts, "sandbox_pmic");
43
44 return 0;
45 }
46 DM_TEST(dm_test_power_pmic_get, UTF_SCAN_FDT);
47
48 /* PMIC get method - MC34708 - for 3 bytes transmission */
dm_test_power_pmic_mc34708_get(struct unit_test_state * uts)49 static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
50 {
51 power_pmic_get(uts, "pmic@41");
52
53 return 0;
54 }
55 DM_TEST(dm_test_power_pmic_mc34708_get, UTF_SCAN_FDT);
56
57 /* Test PMIC I/O */
dm_test_power_pmic_io(struct unit_test_state * uts)58 static int dm_test_power_pmic_io(struct unit_test_state *uts)
59 {
60 const char *name = "sandbox_pmic";
61 uint8_t out_buffer, in_buffer;
62 struct udevice *dev;
63 int reg_count, i;
64
65 ut_assertok(pmic_get(name, &dev));
66
67 reg_count = pmic_reg_count(dev);
68 ut_asserteq(reg_count, SANDBOX_PMIC_REG_COUNT);
69
70 /*
71 * Test PMIC I/O - write and read a loop counter.
72 * usually we can't write to all PMIC's registers in the real hardware,
73 * but we can to the sandbox pmic.
74 */
75 for (i = 0; i < reg_count; i++) {
76 out_buffer = i;
77 ut_assertok(pmic_write(dev, i, &out_buffer, 1));
78 ut_assertok(pmic_read(dev, i, &in_buffer, 1));
79 ut_asserteq(out_buffer, in_buffer);
80 }
81
82 return 0;
83 }
84 DM_TEST(dm_test_power_pmic_io, UTF_SCAN_FDT);
85
86 #define MC34708_PMIC_REG_COUNT 64
87 #define MC34708_PMIC_TEST_VAL 0x125534
dm_test_power_pmic_mc34708_regs_check(struct unit_test_state * uts)88 static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts)
89 {
90 struct udevice *dev;
91 int reg_count;
92
93 ut_assertok(pmic_get("pmic@41", &dev));
94
95 /* Check number of PMIC registers */
96 reg_count = pmic_reg_count(dev);
97 ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT);
98
99 return 0;
100 }
101 DM_TEST(dm_test_power_pmic_mc34708_regs_check, UTF_SCAN_FDT);
102
dm_test_power_pmic_mc34708_rw_val(struct unit_test_state * uts)103 static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
104 {
105 struct udevice *dev;
106 int val;
107
108 ut_assertok(pmic_get("pmic@41", &dev));
109
110 /* Check if single 3 byte read is successful */
111 val = pmic_reg_read(dev, REG_POWER_CTL2);
112 ut_asserteq(val, 0x422100);
113
114 /* Check if RW works */
115 val = 0;
116 ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val));
117 ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL));
118 val = pmic_reg_read(dev, REG_RTC_TIME);
119 ut_asserteq(val, MC34708_PMIC_TEST_VAL);
120
121 pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9);
122 val = pmic_reg_read(dev, REG_POWER_CTL2);
123 ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9));
124
125 return 0;
126 }
127 DM_TEST(dm_test_power_pmic_mc34708_rw_val, UTF_SCAN_FDT);
128