1 /* Raise given exceptions.
2 Copyright (C) 2004-2025 Free Software Foundation, Inc.
3
4 The GNU C Library is free software; you can redistribute it and/or
5 modify it under the terms of the GNU Lesser General Public
6 License as published by the Free Software Foundation; either
7 version 2.1 of the License, or (at your option) any later version.
8
9 The GNU C Library is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 Lesser General Public License for more details.
13
14 You should have received a copy of the GNU Lesser General Public
15 License along with the GNU C Library. If not, see
16 <https://www.gnu.org/licenses/>. */
17
18 #include <fpu_control.h>
19 #include <fenv.h>
20 #include <float.h>
21 #include "arm-features.h"
22
23
24 int
feraiseexcept(int excepts)25 feraiseexcept (int excepts)
26 {
27 /* Fail if a VFP unit isn't present unless nothing needs to be done. */
28 if (!ARM_HAVE_VFP)
29 return (excepts != 0);
30 else
31 {
32 fpu_control_t fpscr;
33 const float fp_zero = 0.0, fp_one = 1.0, fp_max = FLT_MAX,
34 fp_min = FLT_MIN, fp_1e32 = 1.0e32f, fp_two = 2.0,
35 fp_three = 3.0;
36
37 /* Raise exceptions represented by EXPECTS. But we must raise only
38 one signal at a time. It is important that if the overflow/underflow
39 exception and the inexact exception are given at the same time,
40 the overflow/underflow exception follows the inexact exception. After
41 each exception we read from the fpscr, to force the exception to be
42 raised immediately. */
43
44 /* There are additional complications because this file may be compiled
45 without VFP support enabled, and we also can't assume that the
46 assembler has VFP instructions enabled. To get around this we use the
47 generic coprocessor mnemonics and avoid asking GCC to put float values
48 in VFP registers. */
49
50 /* First: invalid exception. */
51 if (FE_INVALID & excepts)
52 __asm__ __volatile__ (
53 "ldc p10, cr0, %1\n\t" /* flds s0, %1 */
54 "cdp p10, 8, cr0, cr0, cr0, 0\n\t" /* fdivs s0, s0, s0 */
55 "mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr) /* fmrx %0, fpscr */
56 : "m" (fp_zero)
57 : "s0");
58
59 /* Next: division by zero. */
60 if (FE_DIVBYZERO & excepts)
61 __asm__ __volatile__ (
62 "ldc p10, cr0, %1\n\t" /* flds s0, %1 */
63 "ldcl p10, cr0, %2\n\t" /* flds s1, %2 */
64 "cdp p10, 8, cr0, cr0, cr0, 1\n\t" /* fdivs s0, s0, s1 */
65 "mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr) /* fmrx %0, fpscr */
66 : "m" (fp_one), "m" (fp_zero)
67 : "s0", "s1");
68
69 /* Next: overflow. */
70 if (FE_OVERFLOW & excepts)
71 /* There's no way to raise overflow without also raising inexact. */
72 __asm__ __volatile__ (
73 "ldc p10, cr0, %1\n\t" /* flds s0, %1 */
74 "ldcl p10, cr0, %2\n\t" /* flds s1, %2 */
75 "cdp p10, 3, cr0, cr0, cr0, 1\n\t" /* fadds s0, s0, s1 */
76 "mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr) /* fmrx %0, fpscr */
77 : "m" (fp_max), "m" (fp_1e32)
78 : "s0", "s1");
79
80 /* Next: underflow. */
81 if (FE_UNDERFLOW & excepts)
82 __asm__ __volatile__ (
83 "ldc p10, cr0, %1\n\t" /* flds s0, %1 */
84 "ldcl p10, cr0, %2\n\t" /* flds s1, %2 */
85 "cdp p10, 8, cr0, cr0, cr0, 1\n\t" /* fdivs s0, s0, s1 */
86 "mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr) /* fmrx %0, fpscr */
87 : "m" (fp_min), "m" (fp_three)
88 : "s0", "s1");
89
90 /* Last: inexact. */
91 if (FE_INEXACT & excepts)
92 __asm__ __volatile__ (
93 "ldc p10, cr0, %1\n\t" /* flds s0, %1 */
94 "ldcl p10, cr0, %2\n\t" /* flds s1, %2 */
95 "cdp p10, 8, cr0, cr0, cr0, 1\n\t" /* fdivs s0, s0, s1 */
96 "mrc p10, 7, %0, cr1, cr0, 0" : "=r" (fpscr) /* fmrx %0, fpscr */
97 : "m" (fp_two), "m" (fp_three)
98 : "s0", "s1");
99
100 /* Success. */
101 return 0;
102 }
103 }
104