1 #ifndef __ASM_MSR_INDEX_H 2 #define __ASM_MSR_INDEX_H 3 4 /* 5 * CPU model specific register (MSR) numbers 6 * 7 * Definitions for an MSR should follow this style: 8 * 9 * #define MSR_$NAME 0x$INDEX 10 * #define $NAME_$FIELD1 (_AC($X, ULL) << $POS1) 11 * #define $NAME_$FIELD2 (_AC($Y, ULL) << $POS2) 12 * 13 * Blocks of related constants should be sorted by MSR index. The constant 14 * names should be as concise as possible, and the bit names may have an 15 * abbreviated name. Exceptions will be considered on a case-by-case basis. 16 */ 17 18 #define MSR_P5_MC_ADDR 0 19 #define MSR_P5_MC_TYPE 0x00000001 20 21 #define MSR_APIC_BASE 0x0000001b 22 #define APIC_BASE_BSP (_AC(1, ULL) << 8) 23 #define APIC_BASE_EXTD (_AC(1, ULL) << 10) 24 #define APIC_BASE_ENABLE (_AC(1, ULL) << 11) 25 #define APIC_BASE_ADDR_MASK _AC(0x000ffffffffff000, ULL) 26 27 #define MSR_TEST_CTRL 0x00000033 28 #define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29) 29 #define TEST_CTRL_SPLITLOCK_DISABLE (_AC(1, ULL) << 31) 30 31 #define MSR_INTEL_CORE_THREAD_COUNT 0x00000035 32 #define MSR_CTC_THREAD_MASK 0x0000ffff 33 #define MSR_CTC_CORE_MASK _AC(0xffff0000, U) 34 35 #define MSR_SPEC_CTRL 0x00000048 36 #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0) 37 #define SPEC_CTRL_STIBP (_AC(1, ULL) << 1) 38 #define SPEC_CTRL_SSBD (_AC(1, ULL) << 2) 39 #define SPEC_CTRL_IPRED_DIS_U (_AC(1, ULL) << 3) 40 #define SPEC_CTRL_IPRED_DIS_S (_AC(1, ULL) << 4) 41 #define SPEC_CTRL_RRSBA_DIS_U (_AC(1, ULL) << 5) 42 #define SPEC_CTRL_RRSBA_DIS_S (_AC(1, ULL) << 6) 43 #define SPEC_CTRL_PSFD (_AC(1, ULL) << 7) 44 #define SPEC_CTRL_DDP_DIS_U (_AC(1, ULL) << 8) 45 #define SPEC_CTRL_BHI_DIS_S (_AC(1, ULL) << 10) 46 47 #define MSR_PRED_CMD 0x00000049 48 #define PRED_CMD_IBPB (_AC(1, ULL) << 0) 49 #define PRED_CMD_SBPB (_AC(1, ULL) << 7) 50 51 #define MSR_PPIN_CTL 0x0000004e 52 #define PPIN_LOCKOUT (_AC(1, ULL) << 0) 53 #define PPIN_ENABLE (_AC(1, ULL) << 1) 54 #define MSR_PPIN 0x0000004f 55 56 #define MSR_MISC_PACKAGE_CTRL 0x000000bc 57 #define PGK_CTRL_ENERGY_FILTER_EN (_AC(1, ULL) << 0) 58 59 #define MSR_PB_OPT_CTRL 0x000000bf 60 #define PB_OPT_IBPB_ALT (_AC(1, ULL) << 0) 61 62 #define MSR_CORE_CAPABILITIES 0x000000cf 63 #define CORE_CAPS_SPLITLOCK_DETECT (_AC(1, ULL) << 5) 64 65 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 66 #define NHM_C3_AUTO_DEMOTE (_AC(1, ULL) << 25) 67 #define NHM_C1_AUTO_DEMOTE (_AC(1, ULL) << 26) 68 #define ATM_LNC_C6_AUTO_DEMOTE (_AC(1, ULL) << 25) 69 #define SNB_C3_AUTO_UNDEMOTE (_AC(1, ULL) << 27) 70 #define SNB_C1_AUTO_UNDEMOTE (_AC(1, ULL) << 28) 71 72 #define MSR_ARCH_CAPABILITIES 0x0000010a 73 #define ARCH_CAPS_RDCL_NO (_AC(1, ULL) << 0) 74 #define ARCH_CAPS_EIBRS (_AC(1, ULL) << 1) 75 #define ARCH_CAPS_RSBA (_AC(1, ULL) << 2) 76 #define ARCH_CAPS_SKIP_L1DFL (_AC(1, ULL) << 3) 77 #define ARCH_CAPS_SSB_NO (_AC(1, ULL) << 4) 78 #define ARCH_CAPS_MDS_NO (_AC(1, ULL) << 5) 79 #define ARCH_CAPS_IF_PSCHANGE_MC_NO (_AC(1, ULL) << 6) 80 #define ARCH_CAPS_TSX_CTRL (_AC(1, ULL) << 7) 81 #define ARCH_CAPS_TAA_NO (_AC(1, ULL) << 8) 82 #define ARCH_CAPS_MISC_PACKAGE_CTRL (_AC(1, ULL) << 10) 83 #define ARCH_CAPS_ENERGY_FILTERING (_AC(1, ULL) << 11) 84 #define ARCH_CAPS_DOITM (_AC(1, ULL) << 12) 85 #define ARCH_CAPS_SBDR_SSDP_NO (_AC(1, ULL) << 13) 86 #define ARCH_CAPS_FBSDP_NO (_AC(1, ULL) << 14) 87 #define ARCH_CAPS_PSDP_NO (_AC(1, ULL) << 15) 88 #define ARCH_CAPS_FB_CLEAR (_AC(1, ULL) << 17) 89 #define ARCH_CAPS_FB_CLEAR_CTRL (_AC(1, ULL) << 18) 90 #define ARCH_CAPS_RRSBA (_AC(1, ULL) << 19) 91 #define ARCH_CAPS_BHI_NO (_AC(1, ULL) << 20) 92 #define ARCH_CAPS_PBRSB_NO (_AC(1, ULL) << 24) 93 #define ARCH_CAPS_GDS_CTRL (_AC(1, ULL) << 25) 94 #define ARCH_CAPS_GDS_NO (_AC(1, ULL) << 26) 95 #define ARCH_CAPS_RFDS_NO (_AC(1, ULL) << 27) 96 #define ARCH_CAPS_RFDS_CLEAR (_AC(1, ULL) << 28) 97 98 #define MSR_FLUSH_CMD 0x0000010b 99 #define FLUSH_CMD_L1D (_AC(1, ULL) << 0) 100 101 #define MSR_TSX_FORCE_ABORT 0x0000010f 102 #define TSX_FORCE_ABORT_RTM (_AC(1, ULL) << 0) 103 #define TSX_CPUID_CLEAR (_AC(1, ULL) << 1) 104 #define TSX_ENABLE_RTM (_AC(1, ULL) << 2) 105 106 #define MSR_TSX_CTRL 0x00000122 107 #define TSX_CTRL_RTM_DISABLE (_AC(1, ULL) << 0) 108 #define TSX_CTRL_CPUID_CLEAR (_AC(1, ULL) << 1) 109 110 #define MSR_MCU_OPT_CTRL 0x00000123 111 #define MCU_OPT_CTRL_RNGDS_MITG_DIS (_AC(1, ULL) << 0) 112 #define MCU_OPT_CTRL_RTM_ALLOW (_AC(1, ULL) << 1) 113 #define MCU_OPT_CTRL_RTM_LOCKED (_AC(1, ULL) << 2) 114 #define MCU_OPT_CTRL_FB_CLEAR_DIS (_AC(1, ULL) << 3) 115 #define MCU_OPT_CTRL_GDS_MIT_DIS (_AC(1, ULL) << 4) 116 #define MCU_OPT_CTRL_GDS_MIT_LOCK (_AC(1, ULL) << 5) 117 118 #define MSR_RTIT_OUTPUT_BASE 0x00000560 119 #define MSR_RTIT_OUTPUT_MASK 0x00000561 120 #define MSR_RTIT_CTL 0x00000570 121 #define RTIT_CTL_TRACE_EN (_AC(1, ULL) << 0) 122 #define RTIT_CTL_CYC_EN (_AC(1, ULL) << 1) 123 #define RTIT_CTL_OS (_AC(1, ULL) << 2) 124 #define RTIT_CTL_USR (_AC(1, ULL) << 3) 125 #define RTIT_CTL_PWR_EVT_EN (_AC(1, ULL) << 4) 126 #define RTIT_CTL_FUP_ON_PTW (_AC(1, ULL) << 5) 127 #define RTIT_CTL_FABRIC_EN (_AC(1, ULL) << 6) 128 #define RTIT_CTL_CR3_FILTER (_AC(1, ULL) << 7) 129 #define RTIT_CTL_TOPA (_AC(1, ULL) << 8) 130 #define RTIT_CTL_MTC_EN (_AC(1, ULL) << 9) 131 #define RTIT_CTL_TSC_EN (_AC(1, ULL) << 10) 132 #define RTIT_CTL_DIS_RETC (_AC(1, ULL) << 11) 133 #define RTIT_CTL_PTW_EN (_AC(1, ULL) << 12) 134 #define RTIT_CTL_BRANCH_EN (_AC(1, ULL) << 13) 135 #define RTIT_CTL_MTC_FREQ (_AC(0xf, ULL) << 14) 136 #define RTIT_CTL_CYC_THRESH (_AC(0xf, ULL) << 19) 137 #define RTIT_CTL_PSB_FREQ (_AC(0xf, ULL) << 24) 138 #define RTIT_CTL_ADDR(n) (_AC(0xf, ULL) << (32 + 4 * (n))) 139 #define MSR_RTIT_STATUS 0x00000571 140 #define RTIT_STATUS_FILTER_EN (_AC(1, ULL) << 0) 141 #define RTIT_STATUS_CONTEXT_EN (_AC(1, ULL) << 1) 142 #define RTIT_STATUS_TRIGGER_EN (_AC(1, ULL) << 2) 143 #define RTIT_STATUS_ERROR (_AC(1, ULL) << 4) 144 #define RTIT_STATUS_STOPPED (_AC(1, ULL) << 5) 145 #define RTIT_STATUS_BYTECNT (_AC(0x1ffff, ULL) << 32) 146 #define MSR_RTIT_CR3_MATCH 0x00000572 147 #define MSR_RTIT_ADDR_A(n) (0x00000580 + (n) * 2) 148 #define MSR_RTIT_ADDR_B(n) (0x00000581 + (n) * 2) 149 150 #define MSR_U_CET 0x000006a0 151 #define MSR_S_CET 0x000006a2 152 #define CET_SHSTK_EN (_AC(1, ULL) << 0) 153 #define CET_WRSS_EN (_AC(1, ULL) << 1) 154 #define CET_ENDBR_EN (_AC(1, ULL) << 2) 155 156 #define MSR_PL0_SSP 0x000006a4 157 #define MSR_PL1_SSP 0x000006a5 158 #define MSR_PL2_SSP 0x000006a6 159 #define MSR_PL3_SSP 0x000006a7 160 #define MSR_ISST 0x000006a8 161 162 #define MSR_PKRS 0x000006e1 163 164 #define MSR_PM_ENABLE 0x00000770 165 #define PM_ENABLE_HWP_ENABLE BIT(0, ULL) 166 167 #define MSR_HWP_CAPABILITIES 0x00000771 168 #define MSR_HWP_INTERRUPT 0x00000773 169 #define MSR_HWP_REQUEST 0x00000774 170 #define MSR_HWP_STATUS 0x00000777 171 172 #define MSR_X2APIC_FIRST 0x00000800 173 #define MSR_X2APIC_LAST 0x000008ff 174 175 #define MSR_X2APIC_TPR 0x00000808 176 #define MSR_X2APIC_PPR 0x0000080a 177 #define MSR_X2APIC_EOI 0x0000080b 178 #define MSR_X2APIC_TMICT 0x00000838 179 #define MSR_X2APIC_TMCCT 0x00000839 180 #define MSR_X2APIC_SELF 0x0000083f 181 182 #define MSR_PASID 0x00000d93 183 #define PASID_PASID_MASK 0x000fffff 184 #define PASID_VALID (_AC(1, ULL) << 31) 185 186 #define MSR_PKG_HDC_CTL 0x00000db0 187 #define PKG_HDC_CTL_HDC_PKG_ENABLE BIT(0, ULL) 188 #define MSR_PM_CTL1 0x00000db1 189 #define PM_CTL1_HDC_ALLOW_BLOCK BIT(0, ULL) 190 191 #define MSR_MCU_CONTROL 0x00001406 192 #define MCU_CONTROL_LOCK (_AC(1, ULL) << 0) 193 #define MCU_CONTROL_DIS_MCU_LOAD (_AC(1, ULL) << 1) 194 #define MCU_CONTROL_EN_SMM_BYPASS (_AC(1, ULL) << 2) 195 196 #define MSR_UARCH_MISC_CTRL 0x00001b01 197 #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0) 198 199 #define MSR_EFER _AC(0xc0000080, U) /* Extended Feature Enable Register */ 200 #define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL Enable */ 201 #define EFER_LME (_AC(1, ULL) << 8) /* Long Mode Enable */ 202 #define EFER_LMA (_AC(1, ULL) << 10) /* Long Mode Active */ 203 #define EFER_NXE (_AC(1, ULL) << 11) /* No Execute Enable */ 204 #define EFER_SVME (_AC(1, ULL) << 12) /* Secure Virtual Machine Enable */ 205 #define EFER_FFXSE (_AC(1, ULL) << 14) /* Fast FXSAVE/FXRSTOR */ 206 #define EFER_AIBRSE (_AC(1, ULL) << 21) /* Automatic IBRS Enable */ 207 208 #define EFER_KNOWN_MASK \ 209 (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \ 210 EFER_AIBRSE) 211 212 #define MSR_STAR _AC(0xc0000081, U) /* legacy mode SYSCALL target */ 213 #define MSR_LSTAR _AC(0xc0000082, U) /* long mode SYSCALL target */ 214 #define MSR_CSTAR _AC(0xc0000083, U) /* compat mode SYSCALL target */ 215 #define MSR_SYSCALL_MASK _AC(0xc0000084, U) /* EFLAGS mask for syscall */ 216 #define MSR_FS_BASE _AC(0xc0000100, U) /* 64bit FS base */ 217 #define MSR_GS_BASE _AC(0xc0000101, U) /* 64bit GS base */ 218 #define MSR_SHADOW_GS_BASE _AC(0xc0000102, U) /* SwapGS GS shadow */ 219 #define MSR_TSC_AUX _AC(0xc0000103, U) /* Auxiliary TSC */ 220 221 #define MSR_K8_SYSCFG _AC(0xc0010010, U) 222 #define SYSCFG_MTRR_FIX_DRAM_EN (_AC(1, ULL) << 18) 223 #define SYSCFG_MTRR_FIX_DRAM_MOD_EN (_AC(1, ULL) << 19) 224 #define SYSCFG_MTRR_VAR_DRAM_EN (_AC(1, ULL) << 20) 225 #define SYSCFG_MTRR_TOM2_EN (_AC(1, ULL) << 21) 226 #define SYSCFG_TOM2_FORCE_WB (_AC(1, ULL) << 22) 227 228 #define MSR_K8_IORR_BASE0 _AC(0xc0010016, U) 229 #define MSR_K8_IORR_MASK0 _AC(0xc0010017, U) 230 #define MSR_K8_IORR_BASE1 _AC(0xc0010018, U) 231 #define MSR_K8_IORR_MASK1 _AC(0xc0010019, U) 232 233 #define MSR_K8_TSEG_BASE _AC(0xc0010112, U) /* AMD doc: SMMAddr */ 234 #define MSR_K8_TSEG_MASK _AC(0xc0010113, U) /* AMD doc: SMMMask */ 235 236 #define MSR_K8_VM_CR _AC(0xc0010114, U) 237 #define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1) 238 #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4) 239 240 #define MSR_VIRT_SPEC_CTRL _AC(0xc001011f, U) /* Layout matches MSR_SPEC_CTRL */ 241 242 #define MSR_AMD_CSTATE_CFG 0xc0010296U 243 244 /* 245 * Legacy MSR constants in need of cleanup. No new MSRs below this comment. 246 */ 247 248 /* Intel MSRs. Some also available on other CPUs */ 249 #define MSR_IA32_PERFCTR0 0x000000c1 250 #define MSR_IA32_A_PERFCTR0 0x000004c1 251 #define MSR_FSB_FREQ 0x000000cd 252 253 #define MSR_MTRRcap 0x000000fe 254 #define MTRRcap_VCNT 0x000000ff 255 256 #define MSR_IA32_BBL_CR_CTL 0x00000119 257 258 #define MSR_IA32_SYSENTER_CS 0x00000174 259 #define MSR_IA32_SYSENTER_ESP 0x00000175 260 #define MSR_IA32_SYSENTER_EIP 0x00000176 261 262 #define MSR_IA32_MCG_CAP 0x00000179 263 #define MSR_IA32_MCG_STATUS 0x0000017a 264 #define MSR_IA32_MCG_CTL 0x0000017b 265 #define MSR_IA32_MCG_EXT_CTL 0x000004d0 266 267 #define MSR_IA32_PEBS_ENABLE 0x000003f1 268 #define MSR_IA32_DS_AREA 0x00000600 269 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 270 /* Lower 6 bits define the format of the address in the LBR stack */ 271 #define MSR_IA32_PERF_CAP_LBR_FORMAT 0x3f 272 273 #define MSR_IA32_BNDCFGS 0x00000d90 274 #define IA32_BNDCFGS_ENABLE 0x00000001 275 #define IA32_BNDCFGS_PRESERVE 0x00000002 276 #define IA32_BNDCFGS_RESERVED 0x00000ffc 277 278 #define MSR_IA32_XSS 0x00000da0 279 280 #define MSR_MTRRfix64K_00000 0x00000250 281 #define MSR_MTRRfix16K_80000 0x00000258 282 #define MSR_MTRRfix16K_A0000 0x00000259 283 #define MSR_MTRRfix4K_C0000 0x00000268 284 #define MSR_MTRRfix4K_C8000 0x00000269 285 #define MSR_MTRRfix4K_D0000 0x0000026a 286 #define MSR_MTRRfix4K_D8000 0x0000026b 287 #define MSR_MTRRfix4K_E0000 0x0000026c 288 #define MSR_MTRRfix4K_E8000 0x0000026d 289 #define MSR_MTRRfix4K_F0000 0x0000026e 290 #define MSR_MTRRfix4K_F8000 0x0000026f 291 #define MSR_MTRRdefType 0x000002ff 292 #define MTRRdefType_FE (1u << 10) 293 #define MTRRdefType_E (1u << 11) 294 295 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 296 #define IA32_DEBUGCTLMSR_LBR (1<<0) /* Last Branch Record */ 297 #define IA32_DEBUGCTLMSR_BTF (1<<1) /* Single Step on Branches */ 298 #define IA32_DEBUGCTLMSR_TR (1<<6) /* Trace Message Enable */ 299 #define IA32_DEBUGCTLMSR_BTS (1<<7) /* Branch Trace Store */ 300 #define IA32_DEBUGCTLMSR_BTINT (1<<8) /* Branch Trace Interrupt */ 301 #define IA32_DEBUGCTLMSR_BTS_OFF_OS (1<<9) /* BTS off if CPL 0 */ 302 #define IA32_DEBUGCTLMSR_BTS_OFF_USR (1<<10) /* BTS off if CPL > 0 */ 303 #define IA32_DEBUGCTLMSR_RTM (1<<15) /* RTM debugging enable */ 304 305 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 306 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 307 #define MSR_IA32_LASTINTFROMIP 0x000001dd 308 #define MSR_IA32_LASTINTTOIP 0x000001de 309 310 #define MSR_IA32_POWER_CTL 0x000001fc 311 312 #define MSR_IA32_MTRR_PHYSBASE(n) (0x00000200 + 2 * (n)) 313 #define MSR_IA32_MTRR_PHYSMASK(n) (0x00000201 + 2 * (n)) 314 315 #define MSR_IA32_CR_PAT 0x00000277 316 #define MSR_IA32_CR_PAT_RESET 0x0007040600070406ULL 317 318 #define MSR_IA32_MC0_CTL 0x00000400 319 #define MSR_IA32_MC0_STATUS 0x00000401 320 #define MSR_IA32_MC0_ADDR 0x00000402 321 #define MSR_IA32_MC0_MISC 0x00000403 322 #define MSR_IA32_MC0_CTL2 0x00000280 323 #define CMCI_EN (1UL<<30) 324 #define CMCI_THRESHOLD_MASK 0x7FFF 325 326 #define MSR_AMD64_MC0_MASK 0xc0010044U 327 328 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 329 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 330 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 331 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 332 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 333 334 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 335 336 /* MSRs & bits used for VMX enabling */ 337 #define MSR_IA32_VMX_BASIC 0x480 338 #define MSR_IA32_VMX_PINBASED_CTLS 0x481 339 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482 340 #define MSR_IA32_VMX_EXIT_CTLS 0x483 341 #define MSR_IA32_VMX_ENTRY_CTLS 0x484 342 #define MSR_IA32_VMX_MISC 0x485 343 #define MSR_IA32_VMX_CR0_FIXED0 0x486 344 #define MSR_IA32_VMX_CR0_FIXED1 0x487 345 #define MSR_IA32_VMX_CR4_FIXED0 0x488 346 #define MSR_IA32_VMX_CR4_FIXED1 0x489 347 #define MSR_IA32_VMX_VMCS_ENUM 0x48a 348 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b 349 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c 350 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48d 351 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e 352 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48f 353 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490 354 #define MSR_IA32_VMX_VMFUNC 0x491 355 #define MSR_IA32_VMX_PROCBASED_CTLS3 0x492 356 357 /* K7/K8 MSRs. Not complete. See the architecture manual for a more 358 complete list. */ 359 #define MSR_K7_EVNTSEL0 0xc0010000U 360 #define MSR_K7_PERFCTR0 0xc0010004U 361 #define MSR_K7_EVNTSEL1 0xc0010001U 362 #define MSR_K7_PERFCTR1 0xc0010005U 363 #define MSR_K7_EVNTSEL2 0xc0010002U 364 #define MSR_K7_PERFCTR2 0xc0010006U 365 #define MSR_K7_EVNTSEL3 0xc0010003U 366 #define MSR_K7_PERFCTR3 0xc0010007U 367 #define MSR_K8_TOP_MEM1 0xc001001aU 368 #define MSR_K8_TOP_MEM2 0xc001001dU 369 370 #define MSR_K8_HWCR 0xc0010015U 371 #define K8_HWCR_TSC_FREQ_SEL (1ULL << 24) 372 #define K8_HWCR_CPUID_USER_DIS (1ULL << 35) 373 374 #define MSR_K7_FID_VID_CTL 0xc0010041U 375 #define MSR_K7_FID_VID_STATUS 0xc0010042U 376 #define MSR_K8_PSTATE_LIMIT 0xc0010061U 377 #define MSR_K8_PSTATE_CTRL 0xc0010062U 378 #define MSR_K8_PSTATE_STATUS 0xc0010063U 379 #define MSR_K8_PSTATE0 0xc0010064U 380 #define MSR_K8_PSTATE1 0xc0010065U 381 #define MSR_K8_PSTATE2 0xc0010066U 382 #define MSR_K8_PSTATE3 0xc0010067U 383 #define MSR_K8_PSTATE4 0xc0010068U 384 #define MSR_K8_PSTATE5 0xc0010069U 385 #define MSR_K8_PSTATE6 0xc001006AU 386 #define MSR_K8_PSTATE7 0xc001006BU 387 #define MSR_K8_ENABLE_C1E 0xc0010055U 388 #define MSR_K8_VM_HSAVE_PA 0xc0010117U 389 390 #define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200U 391 #define MSR_AMD_FAM15H_PERFCTR0 0xc0010201U 392 #define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202U 393 #define MSR_AMD_FAM15H_PERFCTR1 0xc0010203U 394 #define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204U 395 #define MSR_AMD_FAM15H_PERFCTR2 0xc0010205U 396 #define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206U 397 #define MSR_AMD_FAM15H_PERFCTR3 0xc0010207U 398 #define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208U 399 #define MSR_AMD_FAM15H_PERFCTR4 0xc0010209U 400 #define MSR_AMD_FAM15H_EVNTSEL5 0xc001020aU 401 #define MSR_AMD_FAM15H_PERFCTR5 0xc001020bU 402 403 #define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002U 404 #define MSR_AMD_THRM_FEATURE_MASK 0xc0011003U 405 #define MSR_K8_FEATURE_MASK 0xc0011004U 406 #define MSR_K8_EXT_FEATURE_MASK 0xc0011005U 407 408 /* AMD64 MSRs */ 409 #define MSR_AMD64_NB_CFG 0xc001001fU 410 #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 411 #define MSR_AMD64_LS_CFG 0xc0011020U 412 #define MSR_AMD64_IC_CFG 0xc0011021U 413 #define MSR_AMD64_DC_CFG 0xc0011022U 414 #define MSR_AMD64_DE_CFG 0xc0011029U 415 #define AMD64_DE_CFG_LFENCE_SERIALISE (_AC(1, ULL) << 1) 416 #define MSR_AMD64_EX_CFG 0xc001102cU 417 #define MSR_AMD64_BP_CFG 0xc001102eU 418 #define BP_CFG_SPEC_REDUCE (_AC(1, ULL) << 4) 419 #define MSR_AMD64_DE_CFG2 0xc00110e3U 420 421 #define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027U 422 #define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019U 423 #define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101aU 424 #define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101bU 425 426 /* AMD Family10h machine check MSRs */ 427 #define MSR_F10_MC4_MISC1 0xc0000408U 428 #define MSR_F10_MC4_MISC2 0xc0000409U 429 #define MSR_F10_MC4_MISC3 0xc000040AU 430 431 /* AMD Family10h Bus Unit MSRs */ 432 #define MSR_F10_BU_CFG 0xc0011023U 433 #define MSR_F10_BU_CFG2 0xc001102aU 434 435 /* Other AMD Fam10h MSRs */ 436 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058U 437 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 438 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 439 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 440 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 441 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 442 443 /* AMD Microcode MSRs */ 444 #define MSR_AMD_PATCHLEVEL 0x0000008b 445 #define MSR_AMD_PATCHLOADER 0xc0010020U 446 447 /* AMD TSC RATE MSR */ 448 #define MSR_AMD64_TSC_RATIO 0xc0000104U 449 450 /* AMD Lightweight Profiling MSRs */ 451 #define MSR_AMD64_LWP_CFG 0xc0000105U 452 #define MSR_AMD64_LWP_CBADDR 0xc0000106U 453 454 /* AMD OS Visible Workaround MSRs */ 455 #define MSR_AMD_OSVW_ID_LENGTH 0xc0010140U 456 #define MSR_AMD_OSVW_STATUS 0xc0010141U 457 458 /* AMD Protected Processor Inventory Number */ 459 #define MSR_AMD_PPIN_CTL 0xc00102f0U 460 #define MSR_AMD_PPIN 0xc00102f1U 461 462 /* VIA Cyrix defined MSRs*/ 463 #define MSR_VIA_FCR 0x00001107 464 #define MSR_VIA_RNG 0x0000110b 465 466 /* Intel defined MSRs. */ 467 #define MSR_IA32_TSC 0x00000010 468 #define MSR_IA32_PLATFORM_ID 0x00000017 469 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 470 #define MSR_IA32_EBC_FREQUENCY_ID 0x0000002c 471 472 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 473 #define IA32_FEATURE_CONTROL_LOCK 0x0001 474 #define IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX 0x0002 475 #define IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX 0x0004 476 #define IA32_FEATURE_CONTROL_SENTER_PARAM_CTL 0x7f00 477 #define IA32_FEATURE_CONTROL_ENABLE_SENTER 0x8000 478 #define IA32_FEATURE_CONTROL_SGX_ENABLE 0x40000 479 #define IA32_FEATURE_CONTROL_LMCE_ON 0x100000 480 481 #define MSR_IA32_TSC_ADJUST 0x0000003b 482 483 #define MSR_IA32_UCODE_WRITE 0x00000079 484 #define MSR_IA32_UCODE_REV 0x0000008b 485 486 #define MSR_IA32_PERF_STATUS 0x00000198 487 #define MSR_IA32_PERF_CTL 0x00000199 488 489 #define MSR_IA32_MPERF 0x000000e7 490 #define MSR_IA32_APERF 0x000000e8 491 492 #define MSR_IA32_THERM_CONTROL 0x0000019a 493 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 494 #define MSR_IA32_THERM_STATUS 0x0000019c 495 #define MSR_IA32_MISC_ENABLE 0x000001a0 496 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1<<0) 497 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7) 498 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11) 499 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12) 500 #define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18) 501 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22) 502 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23) 503 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (_AC(1, ULL) << 34) 504 #define MSR_IA32_MISC_ENABLE_TURBO_DISENGAGE (_AC(1, ULL) << 38) 505 506 #define MSR_IA32_TSC_DEADLINE 0x000006E0 507 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 508 509 /* Platform Shared Resource MSRs */ 510 #define MSR_IA32_CMT_EVTSEL 0x00000c8d 511 #define MSR_IA32_CMT_EVTSEL_UE_MASK 0x0000ffff 512 #define MSR_IA32_CMT_CTR 0x00000c8e 513 #define MSR_IA32_PSR_ASSOC 0x00000c8f 514 #define MSR_IA32_PSR_L3_QOS_CFG 0x00000c81 515 #define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) 516 #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) 517 #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) 518 #define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) 519 #define MSR_IA32_PSR_MBA_MASK(n) (0x00000d50 + (n)) 520 521 /* Intel Model 6 */ 522 #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) 523 #define MSR_P6_EVNTSEL(n) (0x00000186 + (n)) 524 525 /* P4/Xeon+ specific */ 526 #define MSR_IA32_MCG_EAX 0x00000180 527 #define MSR_IA32_MCG_EBX 0x00000181 528 #define MSR_IA32_MCG_ECX 0x00000182 529 #define MSR_IA32_MCG_EDX 0x00000183 530 #define MSR_IA32_MCG_ESI 0x00000184 531 #define MSR_IA32_MCG_EDI 0x00000185 532 #define MSR_IA32_MCG_EBP 0x00000186 533 #define MSR_IA32_MCG_ESP 0x00000187 534 #define MSR_IA32_MCG_EFLAGS 0x00000188 535 #define MSR_IA32_MCG_EIP 0x00000189 536 #define MSR_IA32_MCG_MISC 0x0000018a 537 #define MSR_IA32_MCG_R8 0x00000190 538 #define MSR_IA32_MCG_R9 0x00000191 539 #define MSR_IA32_MCG_R10 0x00000192 540 #define MSR_IA32_MCG_R11 0x00000193 541 #define MSR_IA32_MCG_R12 0x00000194 542 #define MSR_IA32_MCG_R13 0x00000195 543 #define MSR_IA32_MCG_R14 0x00000196 544 #define MSR_IA32_MCG_R15 0x00000197 545 546 /* Pentium IV performance counter MSRs */ 547 #define MSR_P4_BPU_PERFCTR0 0x00000300 548 #define MSR_P4_BPU_PERFCTR1 0x00000301 549 #define MSR_P4_BPU_PERFCTR2 0x00000302 550 #define MSR_P4_BPU_PERFCTR3 0x00000303 551 #define MSR_P4_MS_PERFCTR0 0x00000304 552 #define MSR_P4_MS_PERFCTR1 0x00000305 553 #define MSR_P4_MS_PERFCTR2 0x00000306 554 #define MSR_P4_MS_PERFCTR3 0x00000307 555 #define MSR_P4_FLAME_PERFCTR0 0x00000308 556 #define MSR_P4_FLAME_PERFCTR1 0x00000309 557 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 558 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 559 #define MSR_P4_IQ_PERFCTR0 0x0000030c 560 #define MSR_P4_IQ_PERFCTR1 0x0000030d 561 #define MSR_P4_IQ_PERFCTR2 0x0000030e 562 #define MSR_P4_IQ_PERFCTR3 0x0000030f 563 #define MSR_P4_IQ_PERFCTR4 0x00000310 564 #define MSR_P4_IQ_PERFCTR5 0x00000311 565 #define MSR_P4_BPU_CCCR0 0x00000360 566 #define MSR_P4_BPU_CCCR1 0x00000361 567 #define MSR_P4_BPU_CCCR2 0x00000362 568 #define MSR_P4_BPU_CCCR3 0x00000363 569 #define MSR_P4_MS_CCCR0 0x00000364 570 #define MSR_P4_MS_CCCR1 0x00000365 571 #define MSR_P4_MS_CCCR2 0x00000366 572 #define MSR_P4_MS_CCCR3 0x00000367 573 #define MSR_P4_FLAME_CCCR0 0x00000368 574 #define MSR_P4_FLAME_CCCR1 0x00000369 575 #define MSR_P4_FLAME_CCCR2 0x0000036a 576 #define MSR_P4_FLAME_CCCR3 0x0000036b 577 #define MSR_P4_IQ_CCCR0 0x0000036c 578 #define MSR_P4_IQ_CCCR1 0x0000036d 579 #define MSR_P4_IQ_CCCR2 0x0000036e 580 #define MSR_P4_IQ_CCCR3 0x0000036f 581 #define MSR_P4_IQ_CCCR4 0x00000370 582 #define MSR_P4_IQ_CCCR5 0x00000371 583 #define MSR_P4_ALF_ESCR0 0x000003ca 584 #define MSR_P4_ALF_ESCR1 0x000003cb 585 #define MSR_P4_BPU_ESCR0 0x000003b2 586 #define MSR_P4_BPU_ESCR1 0x000003b3 587 #define MSR_P4_BSU_ESCR0 0x000003a0 588 #define MSR_P4_BSU_ESCR1 0x000003a1 589 #define MSR_P4_CRU_ESCR0 0x000003b8 590 #define MSR_P4_CRU_ESCR1 0x000003b9 591 #define MSR_P4_CRU_ESCR2 0x000003cc 592 #define MSR_P4_CRU_ESCR3 0x000003cd 593 #define MSR_P4_CRU_ESCR4 0x000003e0 594 #define MSR_P4_CRU_ESCR5 0x000003e1 595 #define MSR_P4_DAC_ESCR0 0x000003a8 596 #define MSR_P4_DAC_ESCR1 0x000003a9 597 #define MSR_P4_FIRM_ESCR0 0x000003a4 598 #define MSR_P4_FIRM_ESCR1 0x000003a5 599 #define MSR_P4_FLAME_ESCR0 0x000003a6 600 #define MSR_P4_FLAME_ESCR1 0x000003a7 601 #define MSR_P4_FSB_ESCR0 0x000003a2 602 #define MSR_P4_FSB_ESCR1 0x000003a3 603 #define MSR_P4_IQ_ESCR0 0x000003ba 604 #define MSR_P4_IQ_ESCR1 0x000003bb 605 #define MSR_P4_IS_ESCR0 0x000003b4 606 #define MSR_P4_IS_ESCR1 0x000003b5 607 #define MSR_P4_ITLB_ESCR0 0x000003b6 608 #define MSR_P4_ITLB_ESCR1 0x000003b7 609 #define MSR_P4_IX_ESCR0 0x000003c8 610 #define MSR_P4_IX_ESCR1 0x000003c9 611 #define MSR_P4_MOB_ESCR0 0x000003aa 612 #define MSR_P4_MOB_ESCR1 0x000003ab 613 #define MSR_P4_MS_ESCR0 0x000003c0 614 #define MSR_P4_MS_ESCR1 0x000003c1 615 #define MSR_P4_PMH_ESCR0 0x000003ac 616 #define MSR_P4_PMH_ESCR1 0x000003ad 617 #define MSR_P4_RAT_ESCR0 0x000003bc 618 #define MSR_P4_RAT_ESCR1 0x000003bd 619 #define MSR_P4_SAAT_ESCR0 0x000003ae 620 #define MSR_P4_SAAT_ESCR1 0x000003af 621 #define MSR_P4_SSU_ESCR0 0x000003be 622 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 623 624 #define MSR_P4_TBPU_ESCR0 0x000003c2 625 #define MSR_P4_TBPU_ESCR1 0x000003c3 626 #define MSR_P4_TC_ESCR0 0x000003c4 627 #define MSR_P4_TC_ESCR1 0x000003c5 628 #define MSR_P4_U2L_ESCR0 0x000003b0 629 #define MSR_P4_U2L_ESCR1 0x000003b1 630 631 /* Netburst (P4) last-branch recording */ 632 #define MSR_P4_LER_FROM_LIP 0x000001d7 633 #define MSR_P4_LER_TO_LIP 0x000001d8 634 #define MSR_P4_LASTBRANCH_TOS 0x000001da 635 #define MSR_P4_LASTBRANCH_0 0x000001db 636 #define NUM_MSR_P4_LASTBRANCH 4 637 #define MSR_P4_LASTBRANCH_0_FROM_LIP 0x00000680 638 #define MSR_P4_LASTBRANCH_0_TO_LIP 0x000006c0 639 #define NUM_MSR_P4_LASTBRANCH_FROM_TO 16 640 641 /* Core 2 and Atom last-branch recording */ 642 #define MSR_C2_LASTBRANCH_TOS 0x000001c9 643 #define MSR_C2_LASTBRANCH_0_FROM_IP 0x00000040 644 #define MSR_C2_LASTBRANCH_0_TO_IP 0x00000060 645 #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4 646 #define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8 647 648 /* Nehalem (and newer) last-branch recording */ 649 #define MSR_NHL_LBR_SELECT 0x000001c8 650 #define MSR_NHL_LASTBRANCH_TOS 0x000001c9 651 652 /* Skylake (and newer) last-branch recording */ 653 #define MSR_SKL_LASTBRANCH_0_FROM_IP 0x00000680 654 #define MSR_SKL_LASTBRANCH_0_TO_IP 0x000006c0 655 #define MSR_SKL_LASTBRANCH_0_INFO 0x00000dc0 656 #define NUM_MSR_SKL_LASTBRANCH 32 657 658 /* Silvermont (and newer) last-branch recording */ 659 #define MSR_SM_LBR_SELECT 0x000001c8 660 #define MSR_SM_LASTBRANCH_TOS 0x000001c9 661 662 /* Goldmont last-branch recording */ 663 #define MSR_GM_LASTBRANCH_0_FROM_IP 0x00000680 664 #define MSR_GM_LASTBRANCH_0_TO_IP 0x000006c0 665 #define NUM_MSR_GM_LASTBRANCH_FROM_TO 32 666 667 /* Intel Core-based CPU performance counters */ 668 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 669 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 670 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 671 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 672 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 673 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 674 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 675 676 /* Intel cpuid spoofing MSRs */ 677 #define MSR_INTEL_MASK_V1_CPUID1 0x00000478 678 679 #define MSR_INTEL_MASK_V2_CPUID1 0x00000130 680 #define MSR_INTEL_MASK_V2_CPUID80000001 0x00000131 681 682 #define MSR_INTEL_MASK_V3_CPUID1 0x00000132 683 #define MSR_INTEL_MASK_V3_CPUID80000001 0x00000133 684 #define MSR_INTEL_MASK_V3_CPUIDD_01 0x00000134 685 686 /* Intel cpuid faulting MSRs */ 687 #define MSR_INTEL_PLATFORM_INFO 0x000000ce 688 #define _MSR_PLATFORM_INFO_CPUID_FAULTING 31 689 #define MSR_PLATFORM_INFO_CPUID_FAULTING (1ULL << _MSR_PLATFORM_INFO_CPUID_FAULTING) 690 691 #define MSR_INTEL_MISC_FEATURES_ENABLES 0x00000140 692 #define _MSR_MISC_FEATURES_CPUID_FAULTING 0 693 #define MSR_MISC_FEATURES_CPUID_FAULTING (1ULL << _MSR_MISC_FEATURES_CPUID_FAULTING) 694 695 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 696 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 697 698 /* Interrupt Response Limit */ 699 #define MSR_PKGC3_IRTL 0x0000060a 700 #define MSR_PKGC6_IRTL 0x0000060b 701 #define MSR_PKGC7_IRTL 0x0000060c 702 #define MSR_PKGC8_IRTL 0x00000633 703 #define MSR_PKGC9_IRTL 0x00000634 704 #define MSR_PKGC10_IRTL 0x00000635 705 706 #endif /* __ASM_MSR_INDEX_H */ 707