1 /****************************************************************************** 2 * config.h 3 * 4 * A Linux-style configuration list. 5 */ 6 7 #ifndef __X86_CONFIG_H__ 8 #define __X86_CONFIG_H__ 9 10 #define CONFIG_PAGING_LEVELS 4 11 12 #define BITS_PER_XEN_ULONG BITS_PER_LONG 13 14 #define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 1 15 #define CONFIG_NUMA_EMU 1 16 17 #define CONFIG_PAGEALLOC_MAX_ORDER (2 * PAGETABLE_ORDER) 18 #define CONFIG_DOMU_MAX_ORDER PAGETABLE_ORDER 19 #define CONFIG_HWDOM_MAX_ORDER 12 20 21 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */ 22 #define CONFIG_X86_L1_CACHE_SHIFT 7 23 24 #define CONFIG_ACPI_CSTATE 1 25 26 #define CONFIG_WATCHDOG 1 27 28 #define CONFIG_MULTIBOOT 1 29 30 #define HZ 100 31 32 #define OPT_CONSOLE_STR "vga" 33 34 /* Linkage for x86 */ 35 #ifdef __ASSEMBLY__ 36 #define CODE_FILL 0x90 37 #endif 38 39 #define NR_hypercalls 64 40 41 #define STACK_ORDER 3 42 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER) 43 44 #define IST_SHSTK_SIZE 1024 45 46 /* Primary stack is restricted to 8kB by guard pages. */ 47 #define PRIMARY_STACK_SIZE 8192 48 49 /* Primary shadow stack is slot 5 of 8, immediately under the primary stack. */ 50 #define PRIMARY_SHSTK_SLOT 5 51 52 /* Return value for zero-size _xmalloc(), distinguished from NULL. */ 53 #define ZERO_BLOCK_PTR ((void *)0xBAD0BAD0BAD0BAD0UL) 54 55 /* Override include/xen/list.h to make these non-canonical addresses. */ 56 #define LIST_POISON1 ((void *)0x0100100100100100UL) 57 #define LIST_POISON2 ((void *)0x0200200200200200UL) 58 59 #include <xen/const.h> 60 61 #define PML4_ENTRY_BITS 39 62 #define PML4_ENTRY_BYTES (_AC(1,UL) << PML4_ENTRY_BITS) 63 #define PML4_ADDR(_slot) \ 64 (((_AC(_slot, UL) >> 8) * _AC(0xffff000000000000,UL)) | \ 65 (_AC(_slot, UL) << PML4_ENTRY_BITS)) 66 67 /* 68 * Memory layout: 69 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255] 70 * Guest-defined use (see below for compatibility mode guests). 71 * 0x0000800000000000 - 0xffff7fffffffffff [16EB] 72 * Inaccessible: current arch only supports 48-bit sign-extended VAs. 73 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256] 74 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE). 75 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256] 76 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE). 77 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257] 78 * ioremap for PCI mmconfig space 79 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258] 80 * Guest linear page table. 81 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259] 82 * Shadow linear page table. 83 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260] 84 * Per-domain mappings (e.g., GDT, LDT). 85 * 0xffff828000000000 - 0xffff82bfffffffff [256GB, 2^38 bytes, PML4:261] 86 * Machine-to-phys translation table. 87 * 0xffff82c000000000 - 0xffff82cfffffffff [64GB, 2^36 bytes, PML4:261] 88 * vmap()/ioremap()/fixmap area. 89 * 0xffff82d000000000 - 0xffff82d03fffffff [1GB, 2^30 bytes, PML4:261] 90 * Compatibility machine-to-phys translation table (CONFIG_PV32). 91 * 0xffff82d040000000 - 0xffff82d07fffffff [1GB, 2^30 bytes, PML4:261] 92 * Xen text, static data, bss. 93 #ifndef CONFIG_BIGMEM 94 * 0xffff82d080000000 - 0xffff82dfffffffff [62GB, PML4:261] 95 * Reserved for future use. 96 * 0xffff82e000000000 - 0xffff82ffffffffff [128GB, 2^37 bytes, PML4:261] 97 * Page-frame information array. 98 * 0xffff830000000000 - 0xffff87ffffffffff [5TB, 5*2^40 bytes, PML4:262-271] 99 * 1:1 direct mapping of all physical memory. 100 #else 101 * 0xffff82d080000000 - 0xffff82ffffffffff [190GB, PML4:261] 102 * Reserved for future use. 103 * 0xffff830000000000 - 0xffff847fffffffff [1.5TB, 3*2^39 bytes, PML4:262-264] 104 * Page-frame information array. 105 * 0xffff848000000000 - 0xffff87ffffffffff [3.5TB, 7*2^39 bytes, PML4:265-271] 106 * 1:1 direct mapping of all physical memory. 107 #endif 108 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511] 109 * PV: Guest-defined use. 110 * 0xffff880000000000 - 0xffffff7fffffffff [119.5TB, PML4:272-510] 111 * HVM/idle: continuation of 1:1 mapping 112 * 0xffffff8000000000 - 0xffffffffffffffff [512GB, 2^39 bytes PML4:511] 113 * HVM/idle: unused 114 * 115 * Compatibility guest area layout: 116 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0] 117 * Guest-defined use. 118 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0] 119 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE). 120 * 0x0000000100000000 - 0x000001ffffffffff [2TB-4GB, PML4:0-3] 121 * Unused / Reserved for future use. 122 * 0x0000020000000000 - 0x0000027fffffffff [512GB, 2^39 bytes, PML4:4] 123 * Mirror of per-domain mappings (for argument translation area; also HVM). 124 * 0x0000028000000000 - 0x00007fffffffffff [125.5TB, PML4:5-255] 125 * Unused / Reserved for future use. 126 */ 127 128 129 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256 130 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271 131 #define ROOT_PAGETABLE_XEN_SLOTS \ 132 (L4_PAGETABLE_ENTRIES - ROOT_PAGETABLE_FIRST_XEN_SLOT - 1) 133 #define ROOT_PAGETABLE_PV_XEN_SLOTS \ 134 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1) 135 136 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */ 137 #define HYPERVISOR_VIRT_START (PML4_ADDR(256)) 138 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16) 139 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */ 140 #define RO_MPT_VIRT_START (PML4_ADDR(256)) 141 #define MPT_VIRT_SIZE (PML4_ENTRY_BYTES / 2) 142 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + MPT_VIRT_SIZE) 143 /* Slot 257: ioremap for PCI mmconfig space for 2048 segments (512GB) 144 * - full 16-bit segment support needs 44 bits 145 * - since PML4 slot has 39 bits, we limit segments to 2048 (11-bits) 146 */ 147 #define PCI_MCFG_VIRT_START (PML4_ADDR(257)) 148 #define PCI_MCFG_VIRT_END (PCI_MCFG_VIRT_START + PML4_ENTRY_BYTES) 149 /* Slot 258: linear page table (guest table). */ 150 #define LINEAR_PT_VIRT_START (PML4_ADDR(258)) 151 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES) 152 /* Slot 259: linear page table (shadow table). */ 153 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259)) 154 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES) 155 /* Slot 260: per-domain mappings (including map cache). */ 156 #define PERDOMAIN_VIRT_START (PML4_ADDR(260)) 157 #define PERDOMAIN_SLOT_MBYTES (PML4_ENTRY_BYTES >> (20 + PAGETABLE_ORDER)) 158 #define PERDOMAIN_SLOTS 3 159 #define PERDOMAIN_VIRT_SLOT(s) (PERDOMAIN_VIRT_START + (s) * \ 160 (PERDOMAIN_SLOT_MBYTES << 20)) 161 /* Slot 4: mirror of per-domain mappings (for compat xlat area accesses). */ 162 #define PERDOMAIN_ALT_VIRT_START PML4_ADDR(4) 163 /* Slot 261: machine-to-phys conversion table (256GB). */ 164 #define RDWR_MPT_VIRT_START (PML4_ADDR(261)) 165 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + MPT_VIRT_SIZE) 166 /* Slot 261: vmap()/ioremap()/fixmap area (64GB). */ 167 #define VMAP_VIRT_START RDWR_MPT_VIRT_END 168 #define VMAP_VIRT_END (VMAP_VIRT_START + GB(64)) 169 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */ 170 #define RDWR_COMPAT_MPT_VIRT_START VMAP_VIRT_END 171 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + GB(1)) 172 /* Slot 261: xen text, static data, bss, per-cpu stubs and executable fixmap (1GB). */ 173 #define XEN_VIRT_START RDWR_COMPAT_MPT_VIRT_END 174 #define XEN_VIRT_END (XEN_VIRT_START + GB(1)) 175 176 #ifndef CONFIG_BIGMEM 177 /* Slot 261: page-frame information array (128GB). */ 178 #define FRAMETABLE_SIZE GB(128) 179 #else 180 /* Slot 262-264: page-frame information array (1.5TB). */ 181 #define FRAMETABLE_SIZE GB(1536) 182 #endif 183 #define FRAMETABLE_VIRT_END DIRECTMAP_VIRT_START 184 #define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) 185 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE) 186 187 #ifndef CONFIG_BIGMEM 188 /* Slot 262-271/510: A direct 1:1 mapping of all of physical memory. */ 189 #define DIRECTMAP_VIRT_START (PML4_ADDR(262)) 190 #define DIRECTMAP_SIZE (PML4_ENTRY_BYTES * (511 - 262)) 191 #else 192 /* Slot 265-271/510: A direct 1:1 mapping of all of physical memory. */ 193 #define DIRECTMAP_VIRT_START (PML4_ADDR(265)) 194 #define DIRECTMAP_SIZE (PML4_ENTRY_BYTES * (511 - 265)) 195 #endif 196 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + DIRECTMAP_SIZE) 197 198 #ifndef __ASSEMBLY__ 199 200 #ifdef CONFIG_PV32 201 202 /* This is not a fixed value, just a lower limit. */ 203 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000 204 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart) 205 206 #else /* !CONFIG_PV32 */ 207 208 #define HYPERVISOR_COMPAT_VIRT_START(d) ((void)(d), 0) 209 210 #endif /* CONFIG_PV32 */ 211 212 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START 213 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000U 214 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \ 215 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2) 216 217 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \ 218 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d)) 219 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U) 220 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \ 221 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1) 222 223 #define COMPAT_LEGACY_MAX_VCPUS XEN_LEGACY_MAX_VCPUS 224 #define COMPAT_HAVE_PV_GUEST_ENTRY XEN_HAVE_PV_GUEST_ENTRY 225 #define COMPAT_HAVE_PV_UPCALL_MASK XEN_HAVE_PV_UPCALL_MASK 226 227 #endif 228 229 #define __HYPERVISOR_CS 0xe008 230 #define __HYPERVISOR_DS64 0x0000 231 #define __HYPERVISOR_DS32 0xe010 232 #define __HYPERVISOR_DS __HYPERVISOR_DS64 233 234 #define SYMBOLS_ORIGIN XEN_VIRT_START 235 236 /* For generic assembly code: use macros to define operation/operand sizes. */ 237 #define __OS "q" /* Operation Suffix */ 238 #define __OP "r" /* Operand Prefix */ 239 240 #ifndef __ASSEMBLY__ 241 extern unsigned long xen_phys_start; 242 #endif 243 244 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */ 245 #define GDT_LDT_VCPU_SHIFT 5 246 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT) 247 #define GDT_LDT_MBYTES PERDOMAIN_SLOT_MBYTES 248 #define MAX_VIRT_CPUS (GDT_LDT_MBYTES << (20-GDT_LDT_VCPU_VA_SHIFT)) 249 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_SLOT(0) 250 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20)) 251 252 /* The address of a particular VCPU's GDT or LDT. */ 253 #define GDT_VIRT_START(v) \ 254 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT)) 255 #define LDT_VIRT_START(v) \ 256 (GDT_VIRT_START(v) + (64*1024)) 257 258 /* map_domain_page() map cache. The second per-domain-mapping sub-area. */ 259 #define MAPCACHE_VCPU_ENTRIES (CONFIG_PAGING_LEVELS * CONFIG_PAGING_LEVELS) 260 #define MAPCACHE_ENTRIES (MAX_VIRT_CPUS * MAPCACHE_VCPU_ENTRIES) 261 #define MAPCACHE_VIRT_START PERDOMAIN_VIRT_SLOT(1) 262 #define MAPCACHE_VIRT_END (MAPCACHE_VIRT_START + \ 263 MAPCACHE_ENTRIES * PAGE_SIZE) 264 265 /* Argument translation area. The third per-domain-mapping sub-area. */ 266 #define ARG_XLAT_VIRT_START PERDOMAIN_VIRT_SLOT(2) 267 /* Allow for at least one guard page (COMPAT_ARG_XLAT_SIZE being 2 pages): */ 268 #define ARG_XLAT_VA_SHIFT (2 + PAGE_SHIFT) 269 #define ARG_XLAT_START(v) \ 270 (ARG_XLAT_VIRT_START + ((v)->vcpu_id << ARG_XLAT_VA_SHIFT)) 271 272 #define ELFSIZE 64 273 274 #define ARCH_CRASH_SAVE_VMCOREINFO 275 276 #endif /* __X86_CONFIG_H__ */ 277