1 /*
2 * cacheattr.c: MTRR and PAT initialisation.
3 *
4 * Copyright (c) 2008, Citrix Systems, Inc.
5 *
6 * Authors:
7 * Keir Fraser <keir@xen.org>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "util.h"
23 #include "config.h"
24
25 #include <xen/asm/x86-defns.h>
26
27 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
28 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
29 #define MSR_MTRRcap 0x00fe
30 #define MSR_MTRRfix64K_00000 0x0250
31 #define MSR_MTRRfix16K_80000 0x0258
32 #define MSR_MTRRfix16K_A0000 0x0259
33 #define MSR_MTRRfix4K_C0000 0x0268
34 #define MSR_MTRRfix4K_C8000 0x0269
35 #define MSR_MTRRfix4K_D0000 0x026a
36 #define MSR_MTRRfix4K_D8000 0x026b
37 #define MSR_MTRRfix4K_E0000 0x026c
38 #define MSR_MTRRfix4K_E8000 0x026d
39 #define MSR_MTRRfix4K_F0000 0x026e
40 #define MSR_MTRRfix4K_F8000 0x026f
41 #define MSR_PAT 0x0277
42 #define MSR_MTRRdefType 0x02ff
43
cpu_phys_addr(void)44 unsigned int cpu_phys_addr(void)
45 {
46 uint32_t eax, ebx, ecx, edx;
47 unsigned int phys_bits = 36;
48 /* Find the physical address size for this CPU. */
49 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
50 if ( eax >= 0x80000008 )
51 {
52 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
53 phys_bits = (uint8_t)eax;
54 }
55
56 return phys_bits;
57 }
58
cacheattr_init(void)59 void cacheattr_init(void)
60 {
61 uint32_t eax, ebx, ecx, edx;
62 uint64_t mtrr_cap, mtrr_def, content, addr_mask;
63 unsigned int i, nr_var_ranges, phys_bits;
64
65 /* Does the CPU support architectural MTRRs? */
66 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
67 if ( !(edx & (1u << 12)) )
68 return;
69
70 phys_bits = cpu_phys_addr();
71
72 printf("%u-bit phys ... ", phys_bits);
73
74 addr_mask = ((1ull << phys_bits) - 1) & ~((1ull << 12) - 1);
75 mtrr_cap = rdmsr(MSR_MTRRcap);
76 mtrr_def = (1u << 11) | X86_MT_WB; /* E, default type WB */
77
78 /* Fixed-range MTRRs supported? */
79 if ( mtrr_cap & (1u << 8) )
80 {
81 #define BCST(mt) ((mt) * 0x0101010101010101ULL)
82 /* 0x00000-0x9ffff: Write Back (WB) */
83 content = BCST(X86_MT_WB);
84 wrmsr(MSR_MTRRfix64K_00000, content);
85 wrmsr(MSR_MTRRfix16K_80000, content);
86
87 /* 0xa0000-0xbffff: Write Combining (WC) */
88 if ( mtrr_cap & (1u << 10) ) /* WC supported? */
89 content = BCST(X86_MT_WC);
90 wrmsr(MSR_MTRRfix16K_A0000, content);
91
92 /* 0xc0000-0xfffff: Write Back (WB) */
93 content = BCST(X86_MT_WB);
94 for ( i = 0; i < 8; i++ )
95 wrmsr(MSR_MTRRfix4K_C0000 + i, content);
96 #undef BCST
97
98 mtrr_def |= 1u << 10; /* FE */
99 printf("fixed MTRRs ... ");
100 }
101
102 /* Variable-range MTRRs supported? */
103 nr_var_ranges = (uint8_t)mtrr_cap;
104 if ( nr_var_ranges != 0 )
105 {
106 uint64_t base = pci_mem_start, size;
107
108 for ( i = 0; (base != pci_mem_end) && (i < nr_var_ranges); i++ )
109 {
110 size = PAGE_SIZE;
111 while ( !(base & size) )
112 size <<= 1;
113 while ( ((base + size) < base) || ((base + size) > pci_mem_end) )
114 size >>= 1;
115
116 wrmsr(MSR_MTRRphysBase(i), base | X86_MT_UC);
117 wrmsr(MSR_MTRRphysMask(i), (~(size - 1) & addr_mask) | (1u << 11));
118
119 base += size;
120 }
121
122 for ( base = pci_hi_mem_start;
123 (base != pci_hi_mem_end) && (i < nr_var_ranges); i++ )
124 {
125 size = PAGE_SIZE;
126 while ( !(base & size) )
127 size <<= 1;
128 while ( (base + size < base) || (base + size > pci_hi_mem_end) )
129 size >>= 1;
130
131 wrmsr(MSR_MTRRphysBase(i), base | X86_MT_UC);
132 wrmsr(MSR_MTRRphysMask(i), (~(size - 1) & addr_mask) | (1u << 11));
133
134 base += size;
135 }
136
137 printf("var MTRRs [%d/%d] ... ", i, nr_var_ranges);
138 }
139
140 wrmsr(MSR_MTRRdefType, mtrr_def);
141 }
142
143 /*
144 * Local variables:
145 * mode: C
146 * c-file-style: "BSD"
147 * c-basic-offset: 4
148 * tab-width: 4
149 * indent-tabs-mode: nil
150 * End:
151 */
152