1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Cache maintenance */
3
4#include <asm/arm32/sysregs.h>
5
6/* dcache_line_size - get the minimum D-cache line size from the CTR register */
7    .macro  dcache_line_size, reg, tmp
8    mrc CP32(\tmp, CTR)             /* read ctr */
9    lsr \tmp, \tmp, #16
10    and \tmp, \tmp, #0xf            /* cache line size encoding */
11    mov \reg, #4                    /* bytes per word */
12    mov \reg, \reg, lsl \tmp        /* actual cache line size */
13    .endm
14
15/*
16 * __invalidate_dcache_area(addr, size)
17 *
18 * Ensure that the data held in the cache for the buffer is invalidated.
19 *
20 * - addr - start address of the buffer
21 * - size - size of the buffer
22 *
23 * Clobbers r0 - r3
24 */
25FUNC(__invalidate_dcache_area)
26    dcache_line_size r2, r3
27    add   r1, r0, r1
28    sub   r3, r2, #1
29    bic   r0, r0, r3
301:  mcr   CP32(r0, DCIMVAC)     /* invalidate D line / unified line */
31    add   r0, r0, r2
32    cmp   r0, r1
33    blo   1b
34    dsb   sy
35    ret
36END(__invalidate_dcache_area)
37
38/*
39 * Local variables:
40 * mode: ASM
41 * indent-tabs-mode: nil
42 * End:
43 */
44