1/*
2 * xen/arch/arm/arm32/debug-scif.inc
3 *
4 * SCIF(A) specific debug code
5 *
6 * Oleksandr Tyshchenko <oleksandr.tyshchenko@globallogic.com>
7 * Copyright (C) 2014, Globallogic.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 * GNU General Public License for more details.
18 */
19
20#include <asm/scif-uart.h>
21
22#ifdef CONFIG_EARLY_UART_SCIF_VERSION_NONE
23#define STATUS_REG    SCIF_SCFSR
24#define TX_FIFO_REG   SCIF_SCFTDR
25#elif CONFIG_EARLY_UART_SCIF_VERSION_A
26#define STATUS_REG    SCIFA_SCASSR
27#define TX_FIFO_REG   SCIFA_SCAFTDR
28#endif
29
30/*
31 * Wait UART to be ready to transmit
32 * rb: register which contains the UART base address
33 * rc: scratch register
34 */
35.macro early_uart_ready rb rc
361:
37        ldrh   \rc, [\rb, #STATUS_REG]   /* Read status register */
38        tst    \rc, #SCFSR_TDFE          /* Check TDFE bit */
39        beq    1b                        /* Wait for the UART to be ready */
40.endm
41
42/*
43 * UART transmit character
44 * rb: register which contains the UART base address
45 * rt: register which contains the character to transmit
46 */
47.macro early_uart_transmit rb rt
48        strb   \rt, [\rb, #TX_FIFO_REG]                  /* Write data register */
49        ldrh   \rt, [\rb, #STATUS_REG]                   /* Read status register */
50        and    \rt, \rt, #(~(SCFSR_TEND | SCFSR_TDFE))   /* Clear TEND and TDFE bits */
51        strh   \rt, [\rb, #STATUS_REG]                   /* Write status register */
52.endm
53
54/*
55 * Local variables:
56 * mode: ASM
57 * indent-tabs-mode: nil
58 * End:
59 */
60