1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * xen/arch/arm/arm64/debug-linflex.inc
4 *
5 * NXP LINFlexD UART specific debug code
6 *
7 * Andrei Cherechesu <andrei.cherechesu@nxp.com>
8 * Copyright 2018, 2021, 2023-2024 NXP
9 */
10
11#include <asm/asm_defns.h>
12#include <asm/linflex-uart.h>
13
14/*
15 * wait LINFlexD UART to be ready to transmit
16 * xb: register which contains the UART base address
17 * c: scratch register number
18 */
19.macro early_uart_ready xb, c
20    ldr   w\c, [\xb, #UARTCR]       /* <= Control Register */
21    and   w\c, w\c, #UARTCR_TFBM    /* Check Buffer/FIFO (0/1) Mode */
22    cbz   w\c, 2f                   /* Buffer Mode => return */
231:
24    ldrb  w\c, [\xb, #UARTSR]       /* <= Status Register */
25    tst   w\c, #UARTSR_DTFTFF       /* FIFO Mode => Check DTF bit */
26    b.ne  1b
272:
28.endm
29
30/*
31 * LINFlexD UART transmit character
32 * xb: register which contains the UART base address
33 * wt: register which contains the character to transmit
34 */
35.macro early_uart_transmit xb, wt
36    strb  \wt, [\xb, #BDRL]
37
38    ldr   \wt, [\xb, #UARTCR]       /* <= Control Register */
39    and   \wt, \wt, #UARTCR_TFBM    /* Check Buffer/FIFO (0/1) Mode */
40    cbnz  \wt, 2f                   /* FIFO Mode => goto exit */
41
423:  /* Buffer Mode */
43    ldrb  \wt, [\xb, #UARTSR]       /* <= Status Register */
44    and   \wt, \wt, #UARTSR_DTFTFF  /* Check Transmission Completed */
45    cbz   \wt, 3b
46
47    ldr   \wt, [\xb, #UARTSR]       /* <= Status Register */
48    orr   \wt, \wt, #UARTSR_DTFTFF  /* Clear DTF bit */
49    str   \wt, [\xb, #UARTSR]
502:
51.endm
52
53/*
54 * Local variables:
55 * mode: ASM
56 * indent-tabs-mode: nil
57 * End:
58 */
59