1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef ARM_ARM32_MPU_H
4 #define ARM_ARM32_MPU_H
5 
6 #ifndef __ASSEMBLY__
7 
8 /*
9  * Unlike arm64, there are no reserved 0 bits beyond base and limit bitfield in
10  * prbar and prlar registers respectively.
11  */
12 #define MPU_REGION_RES0       0x0
13 
14 /* Hypervisor Protection Region Base Address Register */
15 typedef union {
16     struct {
17         unsigned int xn:1;       /* Execute-Never */
18         unsigned int ap_0:1;     /* Access Permission AP[0] */
19         unsigned int ro:1;       /* Access Permission AP[1] */
20         unsigned int sh:2;       /* Shareability */
21         unsigned int res0:1;
22         unsigned int base:26;    /* Base Address */
23     } reg;
24     uint32_t bits;
25 } prbar_t;
26 
27 /* Hypervisor Protection Region Limit Address Register */
28 typedef union {
29     struct {
30         unsigned int en:1;     /* Region enable */
31         unsigned int ai:3;     /* Memory Attribute Index */
32         unsigned int res0:2;
33         unsigned int limit:26; /* Limit Address */
34     } reg;
35     uint32_t bits;
36 } prlar_t;
37 
38 /* MPU Protection Region */
39 typedef struct {
40     prbar_t prbar;
41     prlar_t prlar;
42 } pr_t;
43 
44 #endif /* __ASSEMBLY__ */
45 
46 #endif /* ARM_ARM32_MPU_H */
47 
48 /*
49  * Local variables:
50  * mode: C
51  * c-file-style: "BSD"
52  * c-basic-offset: 4
53  * indent-tabs-mode: nil
54  * End:
55  */
56