1 #ifndef __ARM_ARM32_PAGE_H__
2 #define __ARM_ARM32_PAGE_H__
3
4 #ifndef __ASSEMBLY__
5
6 /* Inline ASM to invalidate dcache on register R (may be an inline asm operand) */
7 #define __invalidate_dcache_one(R) STORE_CP32(R, DCIMVAC)
8
9 /* Inline ASM to flush dcache on register R (may be an inline asm operand) */
10 #define __clean_dcache_one(R) STORE_CP32(R, DCCMVAC)
11
12 /* Inline ASM to clean and invalidate dcache on register R (may be an
13 * inline asm operand) */
14 #define __clean_and_invalidate_dcache_one(R) STORE_CP32(R, DCCIMVAC)
15
16 /*
17 * Invalidate all instruction caches in Inner Shareable domain to PoU.
18 * We also need to flush the branch predictor for ARMv7 as it may be
19 * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b).
20 */
invalidate_icache(void)21 static inline void invalidate_icache(void)
22 {
23 asm volatile (
24 CMD_CP32(ICIALLUIS) /* Flush I-cache. */
25 CMD_CP32(BPIALLIS) /* Flush branch predictor. */
26 : : : "memory");
27
28 dsb(ish); /* Ensure completion of the flush I-cache */
29 isb(); /* Synchronize fetched instruction stream. */
30 }
31
32 /*
33 * Invalidate all instruction caches on the local processor to PoU.
34 * We also need to flush the branch predictor for ARMv7 as it may be
35 * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b).
36 */
invalidate_icache_local(void)37 static inline void invalidate_icache_local(void)
38 {
39 asm volatile (
40 CMD_CP32(ICIALLU) /* Flush I-cache. */
41 CMD_CP32(BPIALL) /* Flush branch predictor. */
42 : : : "memory");
43
44 dsb(nsh); /* Ensure completion of the flush I-cache */
45 isb(); /* Synchronize fetched instruction stream. */
46 }
47
48 /* Ask the MMU to translate a VA for us */
__va_to_par(vaddr_t va)49 static inline uint64_t __va_to_par(vaddr_t va)
50 {
51 uint64_t par, tmp;
52 tmp = READ_CP64(PAR);
53 WRITE_CP32(va, ATS1HR);
54 isb(); /* Ensure result is available. */
55 par = READ_CP64(PAR);
56 WRITE_CP64(tmp, PAR);
57 return par;
58 }
59
60 /* Ask the MMU to translate a Guest VA for us */
gva_to_ma_par(vaddr_t va,unsigned int flags)61 static inline uint64_t gva_to_ma_par(vaddr_t va, unsigned int flags)
62 {
63 uint64_t par, tmp;
64 tmp = READ_CP64(PAR);
65 if ( (flags & GV2M_WRITE) == GV2M_WRITE )
66 WRITE_CP32(va, ATS12NSOPW);
67 else
68 WRITE_CP32(va, ATS12NSOPR);
69 isb(); /* Ensure result is available. */
70 par = READ_CP64(PAR);
71 WRITE_CP64(tmp, PAR);
72 return par;
73 }
gva_to_ipa_par(vaddr_t va,unsigned int flags)74 static inline uint64_t gva_to_ipa_par(vaddr_t va, unsigned int flags)
75 {
76 uint64_t par, tmp;
77 tmp = READ_CP64(PAR);
78 if ( (flags & GV2M_WRITE) == GV2M_WRITE )
79 WRITE_CP32(va, ATS1CPW);
80 else
81 WRITE_CP32(va, ATS1CPR);
82 isb(); /* Ensure result is available. */
83 par = READ_CP64(PAR);
84 WRITE_CP64(tmp, PAR);
85 return par;
86 }
87
88 #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
89
90 #endif /* __ASSEMBLY__ */
91
92 #endif /* __ARM_ARM32_PAGE_H__ */
93
94 /*
95 * Local variables:
96 * mode: C
97 * c-file-style: "BSD"
98 * c-basic-offset: 4
99 * tab-width: 4
100 * indent-tabs-mode: nil
101 * End:
102 */
103