1 #ifndef __ASM_ARM_CPREGS_H 2 #define __ASM_ARM_CPREGS_H 3 4 #include <asm/mpu/cpregs.h> 5 6 /* 7 * AArch32 Co-processor registers. 8 * 9 * Note that AArch64 requires many of these definitions in order to 10 * support 32-bit guests. 11 */ 12 13 #define __HSR_CPREG_c0 0 14 #define __HSR_CPREG_c1 1 15 #define __HSR_CPREG_c2 2 16 #define __HSR_CPREG_c3 3 17 #define __HSR_CPREG_c4 4 18 #define __HSR_CPREG_c5 5 19 #define __HSR_CPREG_c6 6 20 #define __HSR_CPREG_c7 7 21 #define __HSR_CPREG_c8 8 22 #define __HSR_CPREG_c9 9 23 #define __HSR_CPREG_c10 10 24 #define __HSR_CPREG_c11 11 25 #define __HSR_CPREG_c12 12 26 #define __HSR_CPREG_c13 13 27 #define __HSR_CPREG_c14 14 28 #define __HSR_CPREG_c15 15 29 30 #define __HSR_CPREG_0 0 31 #define __HSR_CPREG_1 1 32 #define __HSR_CPREG_2 2 33 #define __HSR_CPREG_3 3 34 #define __HSR_CPREG_4 4 35 #define __HSR_CPREG_5 5 36 #define __HSR_CPREG_6 6 37 #define __HSR_CPREG_7 7 38 39 #define _HSR_CPREG32(cp,op1,crn,crm,op2) \ 40 ((__HSR_CPREG_##crn) << HSR_CP32_CRN_SHIFT) | \ 41 ((__HSR_CPREG_##crm) << HSR_CP32_CRM_SHIFT) | \ 42 ((__HSR_CPREG_##op1) << HSR_CP32_OP1_SHIFT) | \ 43 ((__HSR_CPREG_##op2) << HSR_CP32_OP2_SHIFT) 44 45 #define _HSR_CPREG64(cp,op1,crm) \ 46 ((__HSR_CPREG_##crm) << HSR_CP64_CRM_SHIFT) | \ 47 ((__HSR_CPREG_##op1) << HSR_CP64_OP1_SHIFT) 48 49 /* Encode a register as per HSR ISS pattern */ 50 #define HSR_CPREG32(X...) _HSR_CPREG32(X) 51 #define HSR_CPREG64(X...) _HSR_CPREG64(X) 52 53 /* 54 * Order registers by Coprocessor-> CRn-> Opcode 1-> CRm-> Opcode 2 55 * 56 * This matches the ordering used in the ARM as well as the groupings 57 * which the CP registers are allocated in. 58 * 59 * This is slightly different to the form of the instruction 60 * arguments, which are cp,opc1,crn,crm,opc2. 61 */ 62 63 /* Coprocessor 10 */ 64 65 #define FPSID p10,7,c0,c0,0 /* Floating-Point System ID Register */ 66 #define FPSCR p10,7,c1,c0,0 /* Floating-Point Status and Control Register */ 67 #define MVFR0 p10,7,c7,c0,0 /* Media and VFP Feature Register 0 */ 68 #define MVFR1 p10,7,c6,c0,0 /* Media and VFP Feature Register 1 */ 69 #define MVFR2 p10,7,c5,c0,0 /* Media and VFP Feature Register 2 */ 70 #define FPEXC p10,7,c8,c0,0 /* Floating-Point Exception Control Register */ 71 #define FPINST p10,7,c9,c0,0 /* Floating-Point Instruction Register */ 72 #define FPINST2 p10,7,c10,c0,0 /* Floating-point Instruction Register 2 */ 73 74 /* Coprocessor 14 */ 75 76 /* CP14 0: Debug Register interface */ 77 #define DBGDIDR p14,0,c0,c0,0 /* Debug ID Register */ 78 #define DBGDSCRINT p14,0,c0,c1,0 /* Debug Status and Control Internal */ 79 #define DBGDSCREXT p14,0,c0,c2,2 /* Debug Status and Control External */ 80 #define DBGDTRRXINT p14,0,c0,c5,0 /* Debug Data Transfer Register, Receive */ 81 #define DBGDTRTXINT p14,0,c0,c5,0 /* Debug Data Transfer Register, Transmit */ 82 #define DBGVCR p14,0,c0,c7,0 /* Vector Catch */ 83 #define DBGBVR0 p14,0,c0,c0,4 /* Breakpoint Value 0 */ 84 #define DBGBCR0 p14,0,c0,c0,5 /* Breakpoint Control 0 */ 85 #define DBGWVR0 p14,0,c0,c0,6 /* Watchpoint Value 0 */ 86 #define DBGWCR0 p14,0,c0,c0,7 /* Watchpoint Control 0 */ 87 #define DBGBVR1 p14,0,c0,c1,4 /* Breakpoint Value 1 */ 88 #define DBGBCR1 p14,0,c0,c1,5 /* Breakpoint Control 1 */ 89 #define DBGOSLAR p14,0,c1,c0,4 /* OS Lock Access */ 90 #define DBGOSLSR p14,0,c1,c1,4 /* OS Lock Status Register */ 91 #define DBGOSDLR p14,0,c1,c3,4 /* OS Double Lock */ 92 #define DBGPRCR p14,0,c1,c4,4 /* Debug Power Control Register */ 93 94 /* CP14 CR0: */ 95 #define TEECR p14,6,c0,c0,0 /* ThumbEE Configuration Register */ 96 97 /* CP14 CR1: */ 98 #define DBGDRAR64 p14,0,c1 /* Debug ROM Address Register (64-bit access) */ 99 #define DBGDRAR p14,0,c1,c0,0 /* Debug ROM Address Register (32-bit access) */ 100 #define TEEHBR p14,6,c1,c0,0 /* ThumbEE Handler Base Register */ 101 #define JOSCR p14,7,c1,c0,0 /* Jazelle OS Control Register */ 102 103 /* CP14 CR2: */ 104 #define DBGDSAR64 p14,0,c2 /* Debug Self Address Offset Register (64-bit access) */ 105 #define DBGDSAR p14,0,c2,c0,0 /* Debug Self Address Offset Register (32-bit access) */ 106 #define JMCR p14,7,c2,c0,0 /* Jazelle Main Configuration Register */ 107 108 109 /* Coprocessor 15 */ 110 111 /* CP15 CR0: CPUID and Cache Type Registers */ 112 #define MIDR p15,0,c0,c0,0 /* Main ID Register */ 113 #define CTR p15,0,c0,c0,1 /* Cache Type Register */ 114 #define MPIDR p15,0,c0,c0,5 /* Multiprocessor Affinity Register */ 115 #define ID_PFR0 p15,0,c0,c1,0 /* Processor Feature Register 0 */ 116 #define ID_PFR1 p15,0,c0,c1,1 /* Processor Feature Register 1 */ 117 #define ID_PFR2 p15,0,c0,c3,4 /* Processor Feature Register 2 */ 118 #define ID_DFR0 p15,0,c0,c1,2 /* Debug Feature Register 0 */ 119 #define ID_DFR1 p15,0,c0,c3,5 /* Debug Feature Register 1 */ 120 #define ID_AFR0 p15,0,c0,c1,3 /* Auxiliary Feature Register 0 */ 121 #define ID_MMFR0 p15,0,c0,c1,4 /* Memory Model Feature Register 0 */ 122 #define ID_MMFR1 p15,0,c0,c1,5 /* Memory Model Feature Register 1 */ 123 #define ID_MMFR2 p15,0,c0,c1,6 /* Memory Model Feature Register 2 */ 124 #define ID_MMFR3 p15,0,c0,c1,7 /* Memory Model Feature Register 3 */ 125 #define ID_MMFR4 p15,0,c0,c2,6 /* Memory Model Feature Register 4 */ 126 #define ID_MMFR5 p15,0,c0,c3,6 /* Memory Model Feature Register 5 */ 127 #define ID_ISAR0 p15,0,c0,c2,0 /* ISA Feature Register 0 */ 128 #define ID_ISAR1 p15,0,c0,c2,1 /* ISA Feature Register 1 */ 129 #define ID_ISAR2 p15,0,c0,c2,2 /* ISA Feature Register 2 */ 130 #define ID_ISAR3 p15,0,c0,c2,3 /* ISA Feature Register 3 */ 131 #define ID_ISAR4 p15,0,c0,c2,4 /* ISA Feature Register 4 */ 132 #define ID_ISAR5 p15,0,c0,c2,5 /* ISA Feature Register 5 */ 133 #define ID_ISAR6 p15,0,c0,c2,7 /* ISA Feature Register 6 */ 134 #define CCSIDR p15,1,c0,c0,0 /* Cache Size ID Registers */ 135 #define CLIDR p15,1,c0,c0,1 /* Cache Level ID Register */ 136 #define CSSELR p15,2,c0,c0,0 /* Cache Size Selection Register */ 137 #define VPIDR p15,4,c0,c0,0 /* Virtualization Processor ID Register */ 138 #define VMPIDR p15,4,c0,c0,5 /* Virtualization Multiprocessor ID Register */ 139 140 /* CP15 CR1: System Control Registers */ 141 #define SCTLR p15,0,c1,c0,0 /* System Control Register */ 142 #define ACTLR p15,0,c1,c0,1 /* Auxiliary Control Register */ 143 #define CPACR p15,0,c1,c0,2 /* Coprocessor Access Control Register */ 144 #define SCR p15,0,c1,c1,0 /* Secure Configuration Register */ 145 #define NSACR p15,0,c1,c1,2 /* Non-Secure Access Control Register */ 146 #define HSCTLR p15,4,c1,c0,0 /* Hyp. System Control Register */ 147 #define HCR p15,4,c1,c1,0 /* Hyp. Configuration Register */ 148 #define HDCR p15,4,c1,c1,1 /* Hyp. Debug Configuration Register */ 149 #define HCPTR p15,4,c1,c1,2 /* Hyp. Coprocessor Trap Register */ 150 #define HSTR p15,4,c1,c1,3 /* Hyp. System Trap Register */ 151 152 /* CP15 CR2: Translation Table Base and Control Registers */ 153 #define TTBCR p15,0,c2,c0,2 /* Translation Table Base Control Register */ 154 #define TTBCR2 p15,0,c2,c0,3 /* Translation Table Base Control Register 2 */ 155 #define TTBR0 p15,0,c2 /* Translation Table Base Reg. 0 */ 156 #define TTBR1 p15,1,c2 /* Translation Table Base Reg. 1 */ 157 #define HTTBR p15,4,c2 /* Hyp. Translation Table Base Register */ 158 #define TTBR0_32 p15,0,c2,c0,0 /* 32-bit access to TTBR0 */ 159 #define TTBR1_32 p15,0,c2,c0,1 /* 32-bit access to TTBR1 */ 160 #define HTCR p15,4,c2,c0,2 /* Hyp. Translation Control Register */ 161 #define VTCR p15,4,c2,c1,2 /* Virtualization Translation Control Register */ 162 #define VTTBR p15,6,c2 /* Virtualization Translation Table Base Register */ 163 164 /* CP15 CR3: Domain Access Control Register */ 165 #define DACR p15,0,c3,c0,0 /* Domain Access Control Register */ 166 167 /* CP15 CR4: */ 168 #define ICC_PMR p15,0,c4,c6,0 /* Interrupt Priority Mask Register */ 169 170 /* CP15 CR5: Fault Status Registers */ 171 #define DFSR p15,0,c5,c0,0 /* Data Fault Status Register */ 172 #define IFSR p15,0,c5,c0,1 /* Instruction Fault Status Register */ 173 #define ADFSR p15,0,c5,c1,0 /* Auxiliary Data Fault Status Register */ 174 #define AIFSR p15,0,c5,c1,1 /* Auxiliary Instruction Fault Status Register */ 175 #define HSR p15,4,c5,c2,0 /* Hyp. Syndrome Register */ 176 177 /* CP15 CR6: Fault Address Registers */ 178 #define DFAR p15,0,c6,c0,0 /* Data Fault Address Register */ 179 #define IFAR p15,0,c6,c0,2 /* Instruction Fault Address Register */ 180 #define HDFAR p15,4,c6,c0,0 /* Hyp. Data Fault Address Register */ 181 #define HIFAR p15,4,c6,c0,2 /* Hyp. Instruction Fault Address Register */ 182 #define HPFAR p15,4,c6,c0,4 /* Hyp. IPA Fault Address Register */ 183 184 /* CP15 CR7: Cache and address translation operations */ 185 #define PAR p15,0,c7 /* Physical Address Register */ 186 187 #define ICIALLUIS p15,0,c7,c1,0 /* Invalidate all instruction caches to PoU inner shareable */ 188 #define BPIALLIS p15,0,c7,c1,6 /* Invalidate entire branch predictor array inner shareable */ 189 #define ICIALLU p15,0,c7,c5,0 /* Invalidate all instruction caches to PoU */ 190 #define ICIMVAU p15,0,c7,c5,1 /* Invalidate instruction caches by MVA to PoU */ 191 #define BPIALL p15,0,c7,c5,6 /* Invalidate entire branch predictor array */ 192 #define BPIMVA p15,0,c7,c5,7 /* Invalidate MVA from branch predictor array */ 193 #define DCIMVAC p15,0,c7,c6,1 /* Invalidate data cache line by MVA to PoC */ 194 #define DCISW p15,0,c7,c6,2 /* Invalidate data cache line by set/way */ 195 #define ATS1CPR p15,0,c7,c8,0 /* Address Translation Stage 1. Non-Secure Kernel Read */ 196 #define ATS1CPW p15,0,c7,c8,1 /* Address Translation Stage 1. Non-Secure Kernel Write */ 197 #define ATS1CUR p15,0,c7,c8,2 /* Address Translation Stage 1. Non-Secure User Read */ 198 #define ATS1CUW p15,0,c7,c8,3 /* Address Translation Stage 1. Non-Secure User Write */ 199 #define ATS12NSOPR p15,0,c7,c8,4 /* Address Translation Stage 1+2 Non-Secure Kernel Read */ 200 #define ATS12NSOPW p15,0,c7,c8,5 /* Address Translation Stage 1+2 Non-Secure Kernel Write */ 201 #define ATS12NSOUR p15,0,c7,c8,6 /* Address Translation Stage 1+2 Non-Secure User Read */ 202 #define ATS12NSOUW p15,0,c7,c8,7 /* Address Translation Stage 1+2 Non-Secure User Write */ 203 #define DCCMVAC p15,0,c7,c10,1 /* Clean data or unified cache line by MVA to PoC */ 204 #define DCCSW p15,0,c7,c10,2 /* Clean data cache line by set/way */ 205 #define DCCMVAU p15,0,c7,c11,1 /* Clean data cache line by MVA to PoU */ 206 #define DCCIMVAC p15,0,c7,c14,1 /* Data cache clean and invalidate by MVA */ 207 #define DCCISW p15,0,c7,c14,2 /* Clean and invalidate data cache line by set/way */ 208 #define ATS1HR p15,4,c7,c8,0 /* Address Translation Stage 1 Hyp. Read */ 209 #define ATS1HW p15,4,c7,c8,1 /* Address Translation Stage 1 Hyp. Write */ 210 211 /* CP15 CR8: TLB maintenance operations */ 212 #define TLBIALLIS p15,0,c8,c3,0 /* Invalidate entire TLB innrer shareable */ 213 #define TLBIMVAIS p15,0,c8,c3,1 /* Invalidate unified TLB entry by MVA inner shareable */ 214 #define TLBIASIDIS p15,0,c8,c3,2 /* Invalidate unified TLB by ASID match inner shareable */ 215 #define TLBIMVAAIS p15,0,c8,c3,3 /* Invalidate unified TLB entry by MVA all ASID inner shareable */ 216 #define ITLBIALL p15,0,c8,c5,0 /* Invalidate instruction TLB */ 217 #define ITLBIMVA p15,0,c8,c5,1 /* Invalidate instruction TLB entry by MVA */ 218 #define ITLBIASID p15,0,c8,c5,2 /* Invalidate instruction TLB by ASID match */ 219 #define DTLBIALL p15,0,c8,c6,0 /* Invalidate data TLB */ 220 #define DTLBIMVA p15,0,c8,c6,1 /* Invalidate data TLB entry by MVA */ 221 #define DTLBIASID p15,0,c8,c6,2 /* Invalidate data TLB by ASID match */ 222 #define TLBIALL p15,0,c8,c7,0 /* invalidate unified TLB */ 223 #define TLBIMVA p15,0,c8,c7,1 /* invalidate unified TLB entry by MVA */ 224 #define TLBIASID p15,0,c8,c7,2 /* invalid unified TLB by ASID match */ 225 #define TLBIMVAA p15,0,c8,c7,3 /* invalidate unified TLB entries by MVA all ASID */ 226 #define TLBIALLHIS p15,4,c8,c3,0 /* Invalidate Entire Hyp. Unified TLB inner shareable */ 227 #define TLBIMVAHIS p15,4,c8,c3,1 /* Invalidate Unified Hyp. TLB by MVA inner shareable */ 228 #define TLBIALLNSNHIS p15,4,c8,c3,4 /* Invalidate Entire Non-Secure Non-Hyp. Unified TLB inner shareable */ 229 #define TLBIALLH p15,4,c8,c7,0 /* Invalidate Entire Hyp. Unified TLB */ 230 #define TLBIMVAH p15,4,c8,c7,1 /* Invalidate Unified Hyp. TLB by MVA */ 231 #define TLBIALLNSNH p15,4,c8,c7,4 /* Invalidate Entire Non-Secure Non-Hyp. Unified TLB */ 232 233 /* CP15 CR9: Performance monitors */ 234 #define PMCR p15,0,c9,c12,0 /* Perf. Mon. Control Register */ 235 #define PMCNTENSET p15,0,c9,c12,1 /* Perf. Mon. Count Enable Set register */ 236 #define PMCNTENCLR p15,0,c9,c12,2 /* Perf. Mon. Count Enable Clear register */ 237 #define PMOVSR p15,0,c9,c12,3 /* Perf. Mon. Overflow Flag Status Register */ 238 #define PMSWINC p15,0,c9,c12,4 /* Perf. Mon. Software Increment register */ 239 #define PMSELR p15,0,c9,c12,5 /* Perf. Mon. Event Counter Selection Register */ 240 #define PMCEID0 p15,0,c9,c12,6 /* Perf. Mon. Common Event Identification register 0 */ 241 #define PMCEID1 p15,0,c9,c12,7 /* Perf. Mon. Common Event Identification register 1 */ 242 #define PMCCNTR p15,0,c9,c13,0 /* Perf. Mon. Cycle Count Register */ 243 #define PMXEVTYPER p15,0,c9,c13,1 /* Perf. Mon. Event Type Select Register */ 244 #define PMXEVCNTR p15,0,c9,c13,2 /* Perf. Mon. Event Count Register */ 245 #define PMUSERENR p15,0,c9,c14,0 /* Perf. Mon. User Enable Register */ 246 #define PMINTENSET p15,0,c9,c14,1 /* Perf. Mon. Interrupt Enable Set Register */ 247 #define PMINTENCLR p15,0,c9,c14,2 /* Perf. Mon. Interrupt Enable Clear Register */ 248 #define PMOVSSET p15,0,c9,c14,3 /* Perf. Mon. Overflow Flag Status Set register */ 249 250 /* CP15 CR10: */ 251 #define MAIR0 p15,0,c10,c2,0 /* Memory Attribute Indirection Register 0 AKA PRRR */ 252 #define MAIR1 p15,0,c10,c2,1 /* Memory Attribute Indirection Register 1 AKA NMRR */ 253 #define HMAIR0 p15,4,c10,c2,0 /* Hyp. Memory Attribute Indirection Register 0 */ 254 #define HMAIR1 p15,4,c10,c2,1 /* Hyp. Memory Attribute Indirection Register 1 */ 255 #define AMAIR0 p15,0,c10,c3,0 /* Aux. Memory Attribute Indirection Register 0 */ 256 #define AMAIR1 p15,0,c10,c3,1 /* Aux. Memory Attribute Indirection Register 1 */ 257 258 /* CP15 CR11: DMA Operations for TCM Access */ 259 260 /* CP15 CR12: */ 261 #define ICC_SGI1R p15,0,c12 /* Interrupt Controller SGI Group 1 */ 262 #define ICC_ASGI1R p15,1,c12 /* Interrupt Controller Alias SGI Group 1 Register */ 263 #define ICC_SGI0R p15,2,c12 /* Interrupt Controller SGI Group 0 */ 264 #define VBAR p15,0,c12,c0,0 /* Vector Base Address Register */ 265 #define ICC_DIR p15,0,c12,c11,1 /* Interrupt Controller Deactivate Interrupt Register */ 266 #define HVBAR p15,4,c12,c0,0 /* Hyp. Vector Base Address Register */ 267 268 /* 269 * CP15 CR12: Interrupt Controller Hyp Active Priorities Group 0 Registers, 270 * n = 0 - 3 271 */ 272 #define __AP0Rx(x) p15, 4, c12, c8, x 273 #define ICH_AP0R0 __AP0Rx(0) 274 #define ICH_AP0R1 __AP0Rx(1) 275 #define ICH_AP0R2 __AP0Rx(2) 276 #define ICH_AP0R3 __AP0Rx(3) 277 278 /* 279 * CP15 CR12: Interrupt Controller Hyp Active Priorities Group 1 Registers, 280 * n = 0 - 3 281 */ 282 #define __AP1Rx(x) p15, 4, c12, c9, x 283 #define ICH_AP1R0 __AP1Rx(0) 284 #define ICH_AP1R1 __AP1Rx(1) 285 #define ICH_AP1R2 __AP1Rx(2) 286 #define ICH_AP1R3 __AP1Rx(3) 287 288 #define ICC_IAR1 p15,0,c12,c12,0 /* Interrupt Controller Interrupt Acknowledge Register 1 */ 289 #define ICC_EOIR1 p15,0,c12,c12,1 /* Interrupt Controller End Of Interrupt Register 1 */ 290 #define ICC_BPR1 p15,0,c12,c12,3 /* Interrupt Controller Binary Point Register 1 */ 291 #define ICC_CTLR p15,0,c12,c12,4 /* Interrupt Controller Control Register */ 292 #define ICC_SRE p15,0,c12,c12,5 /* Interrupt Controller System Register Enable register */ 293 #define ICC_IGRPEN1 p15,0,c12,c12,7 /* Interrupt Controller Interrupt Group 1 Enable register */ 294 #define ICC_HSRE p15,4,c12,c9,5 /* Interrupt Controller Hyp System Register Enable register */ 295 #define ICH_HCR p15,4,c12,c11,0 /* Interrupt Controller Hyp Control Register */ 296 #define ICH_VTR p15,4,c12,c11,1 /* Interrupt Controller VGIC Type Register */ 297 #define ICH_MISR p15,4,c12,c11,2 /* Interrupt Controller Maintenance Interrupt State Register */ 298 #define ICH_EISR p15,4,c12,c11,3 /* Interrupt Controller End of Interrupt Status Register */ 299 #define ICH_ELRSR p15,4,c12,c11,5 /* Interrupt Controller Empty List Register Status Register */ 300 #define ICH_VMCR p15,4,c12,c11,7 /* Interrupt Controller Virtual Machine Control Register */ 301 302 /* CP15 CR12: Interrupt Controller List Registers, n = 0 - 15 */ 303 #define __LR0(x) p15, 4, c12, c12, x 304 #define __LR8(x) p15, 4, c12, c13, x 305 306 #define ICH_LR0 __LR0(0) 307 #define ICH_LR1 __LR0(1) 308 #define ICH_LR2 __LR0(2) 309 #define ICH_LR3 __LR0(3) 310 #define ICH_LR4 __LR0(4) 311 #define ICH_LR5 __LR0(5) 312 #define ICH_LR6 __LR0(6) 313 #define ICH_LR7 __LR0(7) 314 #define ICH_LR8 __LR8(0) 315 #define ICH_LR9 __LR8(1) 316 #define ICH_LR10 __LR8(2) 317 #define ICH_LR11 __LR8(3) 318 #define ICH_LR12 __LR8(4) 319 #define ICH_LR13 __LR8(5) 320 #define ICH_LR14 __LR8(6) 321 #define ICH_LR15 __LR8(7) 322 323 /* CP15 CR12: Interrupt Controller List Registers, n = 0 - 15 */ 324 #define __LRC0(x) p15, 4, c12, c14, x 325 #define __LRC8(x) p15, 4, c12, c15, x 326 327 #define ICH_LRC0 __LRC0(0) 328 #define ICH_LRC1 __LRC0(1) 329 #define ICH_LRC2 __LRC0(2) 330 #define ICH_LRC3 __LRC0(3) 331 #define ICH_LRC4 __LRC0(4) 332 #define ICH_LRC5 __LRC0(5) 333 #define ICH_LRC6 __LRC0(6) 334 #define ICH_LRC7 __LRC0(7) 335 #define ICH_LRC8 __LRC8(0) 336 #define ICH_LRC9 __LRC8(1) 337 #define ICH_LRC10 __LRC8(2) 338 #define ICH_LRC11 __LRC8(3) 339 #define ICH_LRC12 __LRC8(4) 340 #define ICH_LRC13 __LRC8(5) 341 #define ICH_LRC14 __LRC8(6) 342 #define ICH_LRC15 __LRC8(7) 343 344 /* CP15 CR13: */ 345 #define FCSEIDR p15,0,c13,c0,0 /* FCSE Process ID Register */ 346 #define CONTEXTIDR p15,0,c13,c0,1 /* Context ID Register */ 347 #define TPIDRURW p15,0,c13,c0,2 /* Software Thread ID, User, R/W */ 348 #define TPIDRURO p15,0,c13,c0,3 /* Software Thread ID, User, R/O */ 349 #define TPIDRPRW p15,0,c13,c0,4 /* Software Thread ID, Priveleged */ 350 #define HTPIDR p15,4,c13,c0,2 /* HYp Software Thread Id Register */ 351 352 /* CP15 CR14: */ 353 #define CNTPCT p15,0,c14 /* Time counter value */ 354 #define CNTFRQ p15,0,c14,c0,0 /* Time counter frequency */ 355 #define CNTKCTL p15,0,c14,c1,0 /* Time counter kernel control */ 356 #define CNTP_TVAL p15,0,c14,c2,0 /* Physical Timer value */ 357 #define CNTP_CTL p15,0,c14,c2,1 /* Physical Timer control register */ 358 #define CNTVCT p15,1,c14 /* Time counter value + offset */ 359 #define CNTP_CVAL p15,2,c14 /* Physical Timer comparator */ 360 #define CNTV_CVAL p15,3,c14 /* Virt. Timer comparator */ 361 #define CNTVOFF p15,4,c14 /* Time counter offset */ 362 #define CNTHCTL p15,4,c14,c1,0 /* Time counter hyp. control */ 363 #define CNTHP_TVAL p15,4,c14,c2,0 /* Hyp. Timer value */ 364 #define CNTHP_CTL p15,4,c14,c2,1 /* Hyp. Timer control register */ 365 #define CNTV_TVAL p15,0,c14,c3,0 /* Virt. Timer value */ 366 #define CNTV_CTL p15,0,c14,c3,1 /* Virt. TImer control register */ 367 #define CNTHP_CVAL p15,6,c14 /* Hyp. Timer comparator */ 368 369 /* CP15 CR15: Implementation Defined Registers */ 370 371 /* Aliases of AArch64 names for use in common code when building for AArch32 */ 372 #ifdef CONFIG_ARM_32 373 /* Alphabetically... */ 374 #define ACTLR_EL1 ACTLR 375 #define AFSR0_EL1 ADFSR 376 #define AFSR1_EL1 AIFSR 377 #define CCSIDR_EL1 CCSIDR 378 #define CLIDR_EL1 CLIDR 379 #define CNTFRQ_EL0 CNTFRQ 380 #define CNTHCTL_EL2 CNTHCTL 381 #define CNTHP_CTL_EL2 CNTHP_CTL 382 #define CNTHP_CVAL_EL2 CNTHP_CVAL 383 #define CNTKCTL_EL1 CNTKCTL 384 #define CNTPCT_EL0 CNTPCT 385 #define CNTP_CTL_EL0 CNTP_CTL 386 #define CNTP_CVAL_EL0 CNTP_CVAL 387 #define CNTVCT_EL0 CNTVCT 388 #define CNTVOFF_EL2 CNTVOFF 389 #define CNTV_CTL_EL0 CNTV_CTL 390 #define CNTV_CVAL_EL0 CNTV_CVAL 391 #define CONTEXTIDR_EL1 CONTEXTIDR 392 #define CPACR_EL1 CPACR 393 #define CPTR_EL2 HCPTR 394 #define CSSELR_EL1 CSSELR 395 #define CTR_EL0 CTR 396 #define DACR32_EL2 DACR 397 #define ESR_EL1 DFSR 398 #define ESR_EL2 HSR 399 #define HCR_EL2 HCR 400 #define HPFAR_EL2 HPFAR 401 #define HSTR_EL2 HSTR 402 #define ICC_BPR1_EL1 ICC_BPR1 403 #define ICC_CTLR_EL1 ICC_CTLR 404 #define ICC_DIR_EL1 ICC_DIR 405 #define ICC_EOIR1_EL1 ICC_EOIR1 406 #define ICC_IGRPEN1_EL1 ICC_IGRPEN1 407 #define ICC_PMR_EL1 ICC_PMR 408 #define ICC_SGI1R_EL1 ICC_SGI1R 409 #define ICC_SRE_EL1 ICC_SRE 410 #define ICC_SRE_EL2 ICC_HSRE 411 #define ICH_AP0R0_EL2 ICH_AP0R0 412 #define ICH_AP0R1_EL2 ICH_AP0R1 413 #define ICH_AP0R2_EL2 ICH_AP0R2 414 #define ICH_AP0R3_EL2 ICH_AP0R3 415 #define ICH_AP1R0_EL2 ICH_AP1R0 416 #define ICH_AP1R1_EL2 ICH_AP1R1 417 #define ICH_AP1R2_EL2 ICH_AP1R2 418 #define ICH_AP1R3_EL2 ICH_AP1R3 419 #define ICH_EISR_EL2 ICH_EISR 420 #define ICH_ELRSR_EL2 ICH_ELRSR 421 #define ICH_HCR_EL2 ICH_HCR 422 #define ICC_IAR1_EL1 ICC_IAR1 423 #define ICH_LR0_EL2 ICH_LR0 424 #define ICH_LR1_EL2 ICH_LR1 425 #define ICH_LR2_EL2 ICH_LR2 426 #define ICH_LR3_EL2 ICH_LR3 427 #define ICH_LR4_EL2 ICH_LR4 428 #define ICH_LR5_EL2 ICH_LR5 429 #define ICH_LR6_EL2 ICH_LR6 430 #define ICH_LR7_EL2 ICH_LR7 431 #define ICH_LR8_EL2 ICH_LR8 432 #define ICH_LR9_EL2 ICH_LR9 433 #define ICH_LR10_EL2 ICH_LR10 434 #define ICH_LR11_EL2 ICH_LR11 435 #define ICH_LR12_EL2 ICH_LR12 436 #define ICH_LR13_EL2 ICH_LR13 437 #define ICH_LR14_EL2 ICH_LR14 438 #define ICH_LR15_EL2 ICH_LR15 439 #define ICH_LRC0_EL2 ICH_LRC0 440 #define ICH_LRC1_EL2 ICH_LRC1 441 #define ICH_LRC2_EL2 ICH_LRC2 442 #define ICH_LRC3_EL2 ICH_LRC3 443 #define ICH_LRC4_EL2 ICH_LRC4 444 #define ICH_LRC5_EL2 ICH_LRC5 445 #define ICH_LRC6_EL2 ICH_LRC6 446 #define ICH_LRC7_EL2 ICH_LRC7 447 #define ICH_LRC8_EL2 ICH_LRC8 448 #define ICH_LRC9_EL2 ICH_LRC9 449 #define ICH_LRC10_EL2 ICH_LRC10 450 #define ICH_LRC11_EL2 ICH_LRC11 451 #define ICH_LRC12_EL2 ICH_LRC12 452 #define ICH_LRC13_EL2 ICH_LRC13 453 #define ICH_LRC14_EL2 ICH_LRC14 454 #define ICH_LRC15_EL2 ICH_LRC15 455 #define ICH_MISR_EL2 ICH_MISR 456 #define ICH_VMCR_EL2 ICH_VMCR 457 #define ICH_VTR_EL2 ICH_VTR 458 #define ID_AFR0_EL1 ID_AFR0 459 #define ID_DFR0_EL1 ID_DFR0 460 #define ID_DFR1_EL1 ID_DFR1 461 #define ID_ISAR0_EL1 ID_ISAR0 462 #define ID_ISAR1_EL1 ID_ISAR1 463 #define ID_ISAR2_EL1 ID_ISAR2 464 #define ID_ISAR3_EL1 ID_ISAR3 465 #define ID_ISAR4_EL1 ID_ISAR4 466 #define ID_ISAR5_EL1 ID_ISAR5 467 #define ID_ISAR6_EL1 ID_ISAR6 468 #define ID_MMFR0_EL1 ID_MMFR0 469 #define ID_MMFR1_EL1 ID_MMFR1 470 #define ID_MMFR2_EL1 ID_MMFR2 471 #define ID_MMFR3_EL1 ID_MMFR3 472 #define ID_MMFR4_EL1 ID_MMFR4 473 #define ID_MMFR5_EL1 ID_MMFR5 474 #define ID_PFR0_EL1 ID_PFR0 475 #define ID_PFR1_EL1 ID_PFR1 476 #define ID_PFR2_EL1 ID_PFR2 477 #define IFSR32_EL2 IFSR 478 #define MDCR_EL2 HDCR 479 #define MIDR_EL1 MIDR 480 #define MPIDR_EL1 MPIDR 481 #define PAR_EL1 PAR 482 #define SCTLR_EL1 SCTLR 483 #define SCTLR_EL2 HSCTLR 484 #define TCR_EL1 TTBCR 485 #define TEECR32_EL1 TEECR 486 #define TEEHBR32_EL1 TEEHBR 487 #define TPIDRRO_EL0 TPIDRURO 488 #define TPIDR_EL0 TPIDRURW 489 #define TPIDR_EL1 TPIDRPRW 490 #define TPIDR_EL2 HTPIDR 491 #define TTBR0_EL1 TTBR0 492 #define TTBR0_EL2 HTTBR 493 #define TTBR1_EL1 TTBR1 494 #define VBAR_EL1 VBAR 495 #define VBAR_EL2 HVBAR 496 #define VMPIDR_EL2 VMPIDR 497 #define VPIDR_EL2 VPIDR 498 #define VTCR_EL2 VTCR 499 #define VTTBR_EL2 VTTBR 500 #define MVFR0_EL1 MVFR0 501 #define MVFR1_EL1 MVFR1 502 #define MVFR2_EL1 MVFR2 503 #endif 504 505 #endif 506 /* 507 * Local variables: 508 * mode: C 509 * c-file-style: "BSD" 510 * c-basic-offset: 4 511 * indent-tabs-mode: nil 512 * End: 513 */ 514