1 /* 2 * xen/include/asm-arm/pl011-uart.h 3 * 4 * Common constant definition between early printk and the UART driver 5 * for the pl011 UART 6 * 7 * Tim Deegan <tim@xen.org> 8 * Copyright (c) 2011 Citrix Systems. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 */ 20 21 #ifndef __ASM_ARM_PL011_H 22 #define __ASM_ARM_PL011_H 23 24 #ifdef __ASSEMBLY__ 25 26 /* 27 * PL011 registers are 8/16-bit wide. However, there are implementations that 28 * can only handle 32-bit accesses. The following macros used in early printk 29 * are defined to distinguish accessors for normal case from 32-bit MMIO one. 30 */ 31 #ifdef CONFIG_EARLY_UART_PL011_MMIO32 32 #define PL011_STRH str 33 #define PL011_STRB str 34 #define PL011_LDRH ldr 35 #else 36 #define PL011_STRH strh 37 #define PL011_STRB strb 38 #define PL011_LDRH ldrh 39 #endif 40 41 #endif /* __ASSEMBLY__ */ 42 43 /* PL011 register addresses */ 44 #define DR (0x00) 45 #define RSR (0x04) 46 #define FR (0x18) 47 #define ILPR (0x20) 48 #define IBRD (0x24) 49 #define FBRD (0x28) 50 #define LCR_H (0x2c) 51 #define CR (0x30) 52 #define IFLS (0x34) 53 #define IMSC (0x38) 54 #define RIS (0x3c) 55 #define MIS (0x40) 56 #define ICR (0x44) 57 #define DMACR (0x48) 58 59 /* CR bits */ 60 #define CTSEN (1<<15) /* automatic CTS hardware flow control */ 61 #define RTSEN (1<<14) /* automatic RTS hardware flow control */ 62 #define RTS (1<<11) /* RTS signal */ 63 #define DTR (1<<10) /* DTR signal */ 64 #define RXE (1<<9) /* Receive enable */ 65 #define TXE (1<<8) /* Transmit enable */ 66 #define UARTEN (1<<0) /* UART enable */ 67 68 /* FR bits */ 69 #define TXFE (1<<7) /* TX FIFO empty */ 70 #define RXFE (1<<4) /* RX FIFO empty */ 71 #define TXFF (1<<5) /* TX FIFO full */ 72 #define RXFF (1<<6) /* RX FIFO full */ 73 #define BUSY (1<<3) /* Transmit is not complete */ 74 75 /* LCR_H bits */ 76 #define SPS (1<<7) /* Stick parity select */ 77 #define WLEN_8 (_AC(0x3, U) << 5) /* 8 bits word length */ 78 #define FEN (1<<4) /* FIFO enable */ 79 #define STP2 (1<<3) /* Two stop bits select */ 80 #define EPS (1<<2) /* Even parity select */ 81 #define PEN (1<<1) /* Parity enable */ 82 #define BRK (1<<0) /* Send break */ 83 84 /* Interrupt bits (IMSC, MIS, ICR) */ 85 #define OEI (1<<10) /* Overrun Error interrupt mask */ 86 #define BEI (1<<9) /* Break Error interrupt mask */ 87 #define PEI (1<<8) /* Parity Error interrupt mask */ 88 #define FEI (1<<7) /* Framing Error interrupt mask */ 89 #define RTI (1<<6) /* Receive Timeout interrupt mask */ 90 #define TXI (1<<5) /* Transmit interrupt mask */ 91 #define RXI (1<<4) /* Receive interrupt mask */ 92 #define DSRMI (1<<3) /* nUARTDSR Modem interrupt mask */ 93 #define DCDMI (1<<2) /* nUARTDCD Modem interrupt mask */ 94 #define CTSMI (1<<1) /* nUARTCTS Modem interrupt mask */ 95 #define RIMI (1<<0) /* nUARTRI Modem interrupt mask */ 96 #define ALLI OEI|BEI|PEI|FEI|RTI|TXI|RXI|DSRMI|DCDMI|CTSMI|RIMI 97 98 #endif /* __ASM_ARM_PL011_H */ 99 100 /* 101 * Local variables: 102 * mode: C 103 * c-file-style: "BSD" 104 * c-basic-offset: 4 105 * indent-tabs-mode: nil 106 * End: 107 */ 108