1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright IBM Corp. 2005, 2006, 2007
4 * Copyright Raptor Engineering, LLC
5 *
6 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
7 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
8 * Timothy Pearson <tpearson@raptorengineering.com>
9 * Shawn Anastasio <sanastasio@raptorengineering.com>
10 */
11
12 #ifndef _ASM_PPC_PROCESSOR_H
13 #define _ASM_PPC_PROCESSOR_H
14
15 #define IOBMP_BYTES 8192
16 #define IOBMP_INVALID_OFFSET 0x8000
17
18 /* Processor Version Register (PVR) field extraction */
19
20 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
21 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
22
23 #define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv))
24
25 /*
26 * IBM has further subdivided the standard PowerPC 16-bit version and
27 * revision subfields of the PVR for the PowerPC 403s into the following:
28 */
29
30 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
31 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
32 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
33 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
34 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
35 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
36
37 /* Processor Version Numbers */
38
39 #define PVR_403GA 0x00200000
40 #define PVR_403GB 0x00200100
41 #define PVR_403GC 0x00200200
42 #define PVR_403GCX 0x00201400
43 #define PVR_405GP 0x40110000
44 #define PVR_STB03XXX 0x40310000
45 #define PVR_NP405H 0x41410000
46 #define PVR_NP405L 0x41610000
47 #define PVR_601 0x00010000
48 #define PVR_602 0x00050000
49 #define PVR_603 0x00030000
50 #define PVR_603e 0x00060000
51 #define PVR_603ev 0x00070000
52 #define PVR_603r 0x00071000
53 #define PVR_604 0x00040000
54 #define PVR_604e 0x00090000
55 #define PVR_604r 0x000A0000
56 #define PVR_620 0x00140000
57 #define PVR_740 0x00080000
58 #define PVR_750 PVR_740
59 #define PVR_740P 0x10080000
60 #define PVR_750P PVR_740P
61 #define PVR_7400 0x000C0000
62 #define PVR_7410 0x800C0000
63 #define PVR_7450 0x80000000
64 #define PVR_8540 0x80200000
65 #define PVR_8560 0x80200000
66 /*
67 * For the 8xx processors, all of them report the same PVR family for
68 * the PowerPC core. The various versions of these processors must be
69 * differentiated by the version number in the Communication Processor
70 * Module (CPM).
71 */
72 #define PVR_821 0x00500000
73 #define PVR_823 PVR_821
74 #define PVR_850 PVR_821
75 #define PVR_860 PVR_821
76 #define PVR_8240 0x00810100
77 #define PVR_8245 0x80811014
78 #define PVR_8260 PVR_8240
79
80 /* 64-bit processors */
81 #define PVR_NORTHSTAR 0x0033
82 #define PVR_PULSAR 0x0034
83 #define PVR_POWER4 0x0035
84 #define PVR_ICESTAR 0x0036
85 #define PVR_SSTAR 0x0037
86 #define PVR_POWER4p 0x0038
87 #define PVR_970 0x0039
88 #define PVR_POWER5 0x003A
89 #define PVR_POWER5p 0x003B
90 #define PVR_970FX 0x003C
91 #define PVR_POWER6 0x003E
92 #define PVR_POWER7 0x003F
93 #define PVR_630 0x0040
94 #define PVR_630p 0x0041
95 #define PVR_970MP 0x0044
96 #define PVR_970GX 0x0045
97 #define PVR_POWER7p 0x004A
98 #define PVR_POWER8E 0x004B
99 #define PVR_POWER8NVL 0x004C
100 #define PVR_POWER8 0x004D
101 #define PVR_POWER9 0x004E
102 #define PVR_POWER10 0x0080
103 #define PVR_BE 0x0070
104 #define PVR_PA6T 0x0090
105
106 /* Exception Definitions */
107 #define EXC_SYSTEM_RESET 0x0100 /* System Reset Interrupt */
108 #define EXC_MACHINE_CHECK 0x0200 /* Machine Check Interrupt */
109 #define EXC_DATA_STORAGE 0x0300 /* Data Storage Interrupt */
110 #define EXC_DATA_SEGMENT 0x0380 /* Data Segment Interrupt */
111 #define EXC_INSN_STORAGE 0x0400 /* Instruction Storage Interrupt */
112 #define EXC_INSN_SEGMENT 0x0480 /* Instruction Segment Interrupt */
113 #define EXC_EXTERNAL 0x0500 /* External Interrupt */
114 #define EXC_ALIGNMENT 0x0600 /* Alignment Interrupt */
115 #define EXC_PROGRAM 0x0700 /* Program Interrupt */
116 #define EXC_FPU_UNAVAIL 0x0800 /* Floating-Point Unavailable Interrupt */
117 #define EXC_DECREMENTER 0x0900 /* Decrementer Interrupt */
118 #define EXC_H_DECREMENTER 0x0980 /* Hypervisor Decrementer Interrupt */
119 #define EXC_PRIV_DOORBELL 0x0A00 /* Directed Privileged Doorbell Interrupt */
120 #define EXC_SYSTEM_CALL 0x0C00 /* System Call Interrupt */
121 #define EXC_TRACE 0x0D00 /* Trace Interrupt */
122 #define EXC_H_DATA_STORAGE 0x0E00 /* Hypervisor Data Storage Interrupt */
123 #define EXC_H_INSN_STORAGE 0x0E20 /* Hypervisor Instruction Storage Interrupt */
124 #define EXC_H_EMUL_ASST 0x0E40 /* Hypervisor Emulation Assistance Interrupt */
125 #define EXC_H_MAINTENANCE 0x0E60 /* Hypervisor Maintenance Interrupt */
126 #define EXC_H_DOORBELL 0x0E80 /* Directed Hypervisor Doorbell Interrupt */
127 #define EXC_H_VIRT 0x0EA0 /* Hypervisor Virtualization Interrupt */
128 #define EXC_PERF_MON 0x0F00 /* Performance Monitor Interrupt */
129 #define EXC_VECTOR_UNAVAIL 0x0F20 /* Vector Unavailable Interrupt */
130 #define EXC_VSX_UNAVAIL 0x0F40 /* VSX Unavailable Interrupt */
131 #define EXC_FACIL_UNAVAIL 0x0F60 /* Facility Unavailable Interrupt */
132 #define EXC_H_FACIL_UNAVAIL 0x0F80 /* Hypervisor Facility Unavailable Interrupt */
133
134 /* Base address of interrupt vector table when LPCR[AIL]=3 */
135 #define AIL_VECTOR_BASE _AC(0xc000000000004000, UL)
136
137 #ifndef __ASSEMBLY__
138
139 #include <xen/types.h>
140
141 /* Macro to adjust thread priority for hardware multithreading */
142 #define HMT_very_low() asm volatile ( "or %r31, %r31, %r31" )
143
144 /* TODO: This isn't correct */
145 #define cpu_to_core(cpu) (0)
146 #define cpu_to_socket(cpu) (0)
147
148 /*
149 * User-accessible registers: most of these need to be saved/restored
150 * for every nested Xen invocation.
151 */
152 struct cpu_user_regs
153 {
154 uint64_t gprs[32];
155 uint64_t lr;
156 uint64_t ctr;
157 uint64_t srr0;
158 uint64_t srr1;
159 uint64_t pc;
160 uint64_t msr;
161 uint64_t fpscr;
162 uint64_t xer;
163 uint64_t hid4; /* debug only */
164 uint64_t dar; /* debug only */
165 uint32_t dsisr; /* debug only */
166 uint32_t cr;
167 uint32_t __pad; /* good spot for another 32bit reg */
168 uint32_t entry_vector;
169 };
170
sync(void)171 static inline void sync(void)
172 {
173 asm volatile ( "sync" );
174 }
175
isync(void)176 static inline void isync(void)
177 {
178 asm volatile ( "isync" );
179 }
180
mfmsr(void)181 static inline unsigned long mfmsr(void)
182 {
183 unsigned long msr;
184 asm volatile ( "mfmsr %0" : "=r" (msr) );
185 return msr;
186 }
187
mtmsrd(unsigned long msr)188 static inline void mtmsrd(unsigned long msr)
189 {
190 asm volatile ( "mtmsrd %0" : : "r" (msr) );
191 }
192
mtspr(uint16_t spr,unsigned long val)193 static inline void mtspr(uint16_t spr, unsigned long val)
194 {
195 asm volatile ( "mtspr %0, %1" : : "K" (spr), "r" (val) );
196 }
197
mfspr(uint16_t spr)198 static inline unsigned long mfspr(uint16_t spr)
199 {
200 unsigned long val;
201 asm volatile ( "mfspr %0, %1" : "=r" (val) : "K" (spr) );
202 return val;
203 }
204
205 /*
206 * panic() isn't available at the moment so an infinite loop will be
207 * used temporarily.
208 * TODO: change it to panic()
209 */
die(void)210 static inline void noreturn die(void)
211 {
212 for ( ; ; )
213 HMT_very_low();
214 }
215
216 /*
217 * Implemented on pre-POWER10 by setting HMT to low then to medium using
218 * the special OR forms. See HMT_very_low above.
219 */
220 #define cpu_relax() asm volatile ( "or %r1, %r1, %r1; or %r2, %r2, %r2" )
221
222 #define dump_execution_state() run_in_exception_handler(show_execution_state)
223
224 #endif /* __ASSEMBLY__ */
225
226 #endif /* _ASM_PPC_PROCESSOR_H */
227