1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * The header taken form Linux 6.4.0-rc1 and is based on
4 * arch/riscv/include/asm/mmio.h with the following changes:
5 * - drop forcing of endianess for read*(), write*() functions as
6 * no matter what CPU endianness, what endianness a particular device
7 * (and hence its MMIO region(s)) is using is entirely independent.
8 * Hence conversion, where necessary, needs to occur at a layer up.
9 * Another one reason to drop endianess conversion is:
10 * https://patchwork.kernel.org/project/linux-riscv/patch/20190411115623.5749-3-hch@lst.de/
11 * One of the answers of the author of the commit:
12 * And we don't know if Linux will be around if that ever changes.
13 * The point is:
14 * a) the current RISC-V spec is LE only
15 * b) the current linux port is LE only except for this little bit
16 * There is no point in leaving just this bitrotting code around. It
17 * just confuses developers, (very very slightly) slows down compiles
18 * and will bitrot. It also won't be any significant help to a future
19 * developer down the road doing a hypothetical BE RISC-V Linux port.
20 * - drop unused argument of __io_ar() macros.
21 * - drop "#define _raw_{read,write}{b,w,l,q} _raw_{read,write}{b,w,l,q}"
22 * as they are unnecessary.
23 * - Adopt the Xen code style for this header, considering that significant
24 * changes are not anticipated in the future.
25 * In the event of any issues, adapting them to Xen style should be easily
26 * manageable.
27 * - drop unnecessary __r variables in macros read*_cpu()
28 * - update inline assembler constraints for addr argument for
29 * __raw_read{b,w,l,q} and __raw_write{b,w,l,q} to tell a compiler that
30 * *addr will be accessed.
31 *
32 * Copyright (C) 1996-2000 Russell King
33 * Copyright (C) 2012 ARM Ltd.
34 * Copyright (C) 2014 Regents of the University of California
35 * Copyright (C) 2024 Vates
36 */
37
38 #ifndef ASM__RISCV__IO_H
39 #define ASM__RISCV__IO_H
40
41 #include <xen/macros.h>
42 #include <xen/types.h>
43
44 void __iomem *ioremap_cache(paddr_t pa, size_t len);
45 void __iomem *ioremap_wc(paddr_t pa, size_t len);
46
47 /* Generic IO read/write. These perform native-endian accesses. */
__raw_writeb(uint8_t val,volatile void __iomem * addr)48 static inline void __raw_writeb(uint8_t val, volatile void __iomem *addr)
49 {
50 asm volatile ( "sb %1, %0"
51 : "=m" (*(volatile uint8_t __force *)addr) : "r" (val) );
52 }
53
__raw_writew(uint16_t val,volatile void __iomem * addr)54 static inline void __raw_writew(uint16_t val, volatile void __iomem *addr)
55 {
56 asm volatile ( "sh %1, %0"
57 : "=m" (*(volatile uint16_t __force *)addr) : "r" (val) );
58 }
59
__raw_writel(uint32_t val,volatile void __iomem * addr)60 static inline void __raw_writel(uint32_t val, volatile void __iomem *addr)
61 {
62 asm volatile ( "sw %1, %0"
63 : "=m" (*(volatile uint32_t __force *)addr) : "r" (val) );
64 }
65
__raw_writeq(uint64_t val,volatile void __iomem * addr)66 static inline void __raw_writeq(uint64_t val, volatile void __iomem *addr)
67 {
68 #ifdef CONFIG_RISCV_32
69 BUILD_BUG_ON("unimplemented");
70 #else
71 asm volatile ( "sd %1, %0"
72 : "=m" (*(volatile uint64_t __force *)addr) : "r" (val) );
73 #endif
74 }
75
__raw_readb(const volatile void __iomem * addr)76 static inline uint8_t __raw_readb(const volatile void __iomem *addr)
77 {
78 uint8_t val;
79
80 asm volatile ( "lb %0, %1" : "=r" (val)
81 : "m" (*(const volatile uint8_t __force *)addr) );
82 return val;
83 }
84
__raw_readw(const volatile void __iomem * addr)85 static inline uint16_t __raw_readw(const volatile void __iomem *addr)
86 {
87 uint16_t val;
88
89 asm volatile ( "lh %0, %1" : "=r" (val)
90 : "m" (*(const volatile uint16_t __force *)addr) );
91 return val;
92 }
93
__raw_readl(const volatile void __iomem * addr)94 static inline uint32_t __raw_readl(const volatile void __iomem *addr)
95 {
96 uint32_t val;
97
98 asm volatile ( "lw %0, %1" : "=r" (val)
99 : "m" (*(const volatile uint32_t __force *)addr) );
100 return val;
101 }
102
__raw_readq(const volatile void __iomem * addr)103 static inline uint64_t __raw_readq(const volatile void __iomem *addr)
104 {
105 uint64_t val;
106
107 #ifdef CONFIG_RISCV_32
108 BUILD_BUG_ON("unimplemented");
109 #else
110 asm volatile ( "ld %0, %1" : "=r" (val)
111 : "m" (*(const volatile uint64_t __force *)addr) );
112 #endif
113
114 return val;
115 }
116
117
118 /*
119 * Unordered I/O memory access primitives. These are even more relaxed than
120 * the relaxed versions, as they don't even order accesses between successive
121 * operations to the I/O regions.
122 */
123 #define readb_cpu(c) __raw_readb(c)
124 #define readw_cpu(c) __raw_readw(c)
125 #define readl_cpu(c) __raw_readl(c)
126 #define readq_cpu(c) __raw_readq(c)
127
128 #define writeb_cpu(v, c) __raw_writeb(v, c)
129 #define writew_cpu(v, c) __raw_writew(v, c)
130 #define writel_cpu(v, c) __raw_writel(v, c)
131 #define writeq_cpu(v, c) __raw_writeq(v, c)
132
133 /*
134 * I/O memory access primitives. Reads are ordered relative to any
135 * following Normal memory access. Writes are ordered relative to any prior
136 * Normal memory access. The memory barriers here are necessary as RISC-V
137 * doesn't define any ordering between the memory space and the I/O space.
138 */
139 #define __io_br() do { } while (0)
140 #define __io_ar() asm volatile ( "fence i,r" : : : "memory" );
141 #define __io_bw() asm volatile ( "fence w,o" : : : "memory" );
142 #define __io_aw() do { } while (0)
143
144 #define readb(c) ({ uint8_t v_; __io_br(); v_ = readb_cpu(c); __io_ar(); v_; })
145 #define readw(c) ({ uint16_t v_; __io_br(); v_ = readw_cpu(c); __io_ar(); v_; })
146 #define readl(c) ({ uint32_t v_; __io_br(); v_ = readl_cpu(c); __io_ar(); v_; })
147 #define readq(c) ({ uint64_t v_; __io_br(); v_ = readq_cpu(c); __io_ar(); v_; })
148
149 #define writeb(v, c) ({ __io_bw(); writeb_cpu(v, c); __io_aw(); })
150 #define writew(v, c) ({ __io_bw(); writew_cpu(v, c); __io_aw(); })
151 #define writel(v, c) ({ __io_bw(); writel_cpu(v, c); __io_aw(); })
152 #define writeq(v, c) ({ __io_bw(); writeq_cpu(v, c); __io_aw(); })
153
154 #endif /* ASM__RISCV__IO_H */
155
156 /*
157 * Local variables:
158 * mode: C
159 * c-file-style: "BSD"
160 * c-basic-offset: 4
161 * indent-tabs-mode: nil
162 * End:
163 */
164