1 /* 2 * Machine dependent access functions for RTC registers. 3 */ 4 #ifndef _ASM_MC146818RTC_H 5 #define _ASM_MC146818RTC_H 6 7 #include <asm/io.h> 8 #include <xen/spinlock.h> 9 10 extern spinlock_t rtc_lock; /* serialize CMOS RAM access */ 11 12 struct domain; 13 bool is_cmos_port(unsigned int port, unsigned int bytes, 14 const struct domain *d); 15 16 /********************************************************************** 17 * register summary 18 **********************************************************************/ 19 #define RTC_SECONDS 0 20 #define RTC_SECONDS_ALARM 1 21 #define RTC_MINUTES 2 22 #define RTC_MINUTES_ALARM 3 23 #define RTC_HOURS 4 24 #define RTC_HOURS_ALARM 5 25 /* RTC_*_alarm is always true if 2 MSBs are set */ 26 # define RTC_ALARM_DONT_CARE 0xC0 27 28 #define RTC_DAY_OF_WEEK 6 29 #define RTC_DAY_OF_MONTH 7 30 #define RTC_MONTH 8 31 #define RTC_YEAR 9 32 33 /* control registers - Moto names 34 */ 35 #define RTC_REG_A 10 36 #define RTC_REG_B 11 37 #define RTC_REG_C 12 38 #define RTC_REG_D 13 39 40 /********************************************************************** 41 * register details 42 **********************************************************************/ 43 #define RTC_FREQ_SELECT RTC_REG_A 44 45 /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, 46 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, 47 * totalling to a max high interval of 2.228 ms. 48 */ 49 # define RTC_UIP 0x80 50 # define RTC_DIV_CTL 0x70 51 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ 52 # define RTC_REF_CLCK_4MHZ 0x00 53 # define RTC_REF_CLCK_1MHZ 0x10 54 # define RTC_REF_CLCK_32KHZ 0x20 55 /* 2 values for divider stage reset, others for "testing purposes only" */ 56 # define RTC_DIV_RESET1 0x60 57 # define RTC_DIV_RESET2 0x70 58 /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ 59 # define RTC_RATE_SELECT 0x0F 60 61 /**********************************************************************/ 62 #define RTC_CONTROL RTC_REG_B 63 # define RTC_SET 0x80 /* disable updates for clock setting */ 64 # define RTC_PIE 0x40 /* periodic interrupt enable */ 65 # define RTC_AIE 0x20 /* alarm interrupt enable */ 66 # define RTC_UIE 0x10 /* update-finished interrupt enable */ 67 # define RTC_SQWE 0x08 /* enable square-wave output */ 68 # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ 69 # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ 70 # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ 71 72 /**********************************************************************/ 73 #define RTC_INTR_FLAGS RTC_REG_C 74 /* caution - cleared by read */ 75 # define RTC_IRQF 0x80 /* any of the following 3 is active */ 76 # define RTC_PF 0x40 77 # define RTC_AF 0x20 78 # define RTC_UF 0x10 79 80 /**********************************************************************/ 81 #define RTC_VALID RTC_REG_D 82 # define RTC_VRT 0x80 /* valid RAM and time */ 83 /**********************************************************************/ 84 85 /* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) 86 * determines if the following two #defines are needed 87 */ 88 #ifndef BCD_TO_BIN 89 #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) 90 #endif 91 92 #ifndef BIN_TO_BCD 93 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) 94 #endif 95 96 97 #ifndef RTC_PORT 98 #define RTC_PORT(x) (0x70 + (x)) 99 #define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ 100 #endif 101 102 /* 103 * The yet supported machines all access the RTC index register via 104 * an ISA port access but the way to access the date register differs ... 105 */ 106 #define CMOS_READ(addr) ({ \ 107 outb_p((addr),RTC_PORT(0)); \ 108 inb_p(RTC_PORT(1)); \ 109 }) 110 #define CMOS_WRITE(val, addr) ({ \ 111 outb_p((addr),RTC_PORT(0)); \ 112 outb_p((val),RTC_PORT(1)); \ 113 }) 114 115 #define RTC_IRQ 8 116 117 unsigned int rtc_guest_read(unsigned int port); 118 void rtc_guest_write(unsigned int port, unsigned int data); 119 120 #endif /* _ASM_MC146818RTC_H */ 121