1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef X86_TIME_H
3 #define X86_TIME_H
4
5 #include <asm/tsc.h>
6
7 typedef u64 cycles_t;
8
9 extern bool disable_tsc_sync;
10
get_cycles(void)11 static inline cycles_t get_cycles(void)
12 {
13 return rdtsc_ordered();
14 }
15
16 unsigned long
17 mktime (unsigned int year, unsigned int mon,
18 unsigned int day, unsigned int hour,
19 unsigned int min, unsigned int sec);
20
21 int time_suspend(void);
22 int time_resume(void);
23
24 void init_percpu_time(void);
25 void time_latch_stamps(void);
26
27 struct ioreq;
28 int hwdom_pit_access(struct ioreq *ioreq);
29
30 int cpu_frequency_change(u64 freq);
31
32 void cf_check pit_broadcast_enter(void);
33 void cf_check pit_broadcast_exit(void);
34 int pit_broadcast_is_available(void);
35
36 uint64_t cf_check acpi_pm_tick_to_ns(uint64_t ticks);
37
38 uint64_t tsc_ticks2ns(uint64_t ticks);
39
40 struct cpu_user_regs;
41 uint64_t pv_soft_rdtsc(const struct vcpu *v, const struct cpu_user_regs *regs);
42 uint64_t gtime_to_gtsc(const struct domain *d, uint64_t time);
43 uint64_t gtsc_to_gtime(const struct domain *d, uint64_t tsc);
44
45 int tsc_set_info(struct domain *d, uint32_t tsc_mode, uint64_t elapsed_nsec,
46 uint32_t gtsc_khz, uint32_t incarnation);
47
48 void tsc_get_info(struct domain *d, uint32_t *tsc_mode, uint64_t *elapsed_nsec,
49 uint32_t *gtsc_khz, uint32_t *incarnation);
50
51 void force_update_vcpu_system_time(struct vcpu *v);
52
53 bool clocksource_is_tsc(void);
54 int host_tsc_is_safe(void);
55 u64 stime2tsc(s_time_t stime);
56
57 struct time_scale;
58 void set_time_scale(struct time_scale *ts, u64 ticks_per_sec);
59 u64 scale_delta(u64 delta, const struct time_scale *scale);
60
61 /* Programmable Interval Timer (8254) */
62
63 /* Timer Control Word */
64 #define PIT_TCW_CH(n) ((n) << 6)
65 /* Lower bits also Timer Status. */
66 #define PIT_RW_MSB (1 << 5)
67 #define PIT_RW_LSB (1 << 4)
68 #define PIT_RW_LSB_MSB (PIT_RW_LSB | PIT_RW_MSB)
69 #define PIT_MODE_EOC (0 << 1)
70 #define PIT_MODE_ONESHOT (1 << 1)
71 #define PIT_MODE_RATE_GEN (2 << 1)
72 #define PIT_MODE_SQUARE_WAVE (3 << 1)
73 #define PIT_MODE_SW_STROBE (4 << 1)
74 #define PIT_MODE_HW_STROBE (5 << 1)
75 #define PIT_BINARY (0 << 0)
76 #define PIT_BCD (1 << 0)
77
78 /* Read Back Command */
79 #define PIT_RDB PIT_TCW_CH(3)
80 #define PIT_RDB_NO_COUNT (1 << 5)
81 #define PIT_RDB_NO_STATUS (1 << 4)
82 #define PIT_RDB_CH2 (1 << 3)
83 #define PIT_RDB_CH1 (1 << 2)
84 #define PIT_RDB_CH0 (1 << 1)
85 #define PIT_RDB_RSVD (1 << 0)
86
87 /* Counter Latch Command */
88 #define PIT_LTCH_CH(n) PIT_TCW_CH(n)
89
90 /* Timer Status */
91 #define PIT_STATUS_OUT_PIN (1 << 7)
92 #define PIT_STATUS_NULL_COUNT (1 << 6)
93 /* Lower bits match Timer Control Word. */
94
95 #endif /* X86_TIME_H */
96