Lines Matching refs:root
89 struct clock_control_bl61x_root_config root; member
827 clock_control_bl61x_select_PLL(data->root.pll_select); in clock_control_bl61x_init_root_as_wifipll()
831 if (data->root.pll_select == 1) { in clock_control_bl61x_init_root_as_wifipll()
833 } else if (data->root.pll_select == 2) { in clock_control_bl61x_init_root_as_wifipll()
926 ret = clock_bflb_set_root_clock_dividers(data->root.divider - 1, data->bclk.divider - 1); in clock_control_bl61x_update_root()
931 if (data->root.source == bl61x_clkid_clk_wifipll) { in clock_control_bl61x_update_root()
933 } else if (data->root.source == bl61x_clkid_clk_crystal) { in clock_control_bl61x_update_root()
1056 if (data->root.source == bl61x_clkid_clk_rc32m) { in clock_control_bl61x_on()
1060 data->root.source = bl61x_clkid_clk_rc32m; in clock_control_bl61x_on()
1064 if (data->root.source == bl61x_clkid_clk_crystal) { in clock_control_bl61x_on()
1067 oldroot = data->root.source; in clock_control_bl61x_on()
1068 data->root.source = bl61x_clkid_clk_crystal; in clock_control_bl61x_on()
1071 data->root.source = oldroot; in clock_control_bl61x_on()
1075 if (data->root.source == bl61x_clkid_clk_wifipll) { in clock_control_bl61x_on()
1078 oldroot = data->root.source; in clock_control_bl61x_on()
1079 data->root.source = bl61x_clkid_clk_wifipll; in clock_control_bl61x_on()
1082 data->root.source = oldroot; in clock_control_bl61x_on()
1216 .root = {
1217 #if CLK_SRC_IS(root, wifipll_320)
1218 .pll_select = DT_CLOCKS_CELL(DT_INST_CLOCKS_CTLR_BY_NAME(0, root), select) & 0xF,
1220 #elif CLK_SRC_IS(root, aupll_div1)
1221 .pll_select = DT_CLOCKS_CELL(DT_INST_CLOCKS_CTLR_BY_NAME(0, root), select) & 0xF,
1223 #elif CLK_SRC_IS(root, crystal)
1228 .divider = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, root), divider),
1237 #if CLK_SRC_IS(root, wifipll_320)
1238 .overclock = DT_CLOCKS_CELL(DT_INST_CLOCKS_CTLR_BY_NAME(0, root), select) & 0x10,
1276 || CLK_SRC_IS(root, crystal)
1280 BUILD_ASSERT(CLK_SRC_IS(root, wifipll_320)
1284 BUILD_ASSERT(CLK_SRC_IS(root, aupll_div1)