Lines Matching refs:devcfg
280 const struct xec_pcr_config * const devcfg = dev->config; in soc_clk32_init() local
281 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base; in soc_clk32_init()
282 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in soc_clk32_init()
314 rc = pll_wait_lock_periph(pcr, devcfg->xtal_enable_delay_ms); in soc_clk32_init()
433 const struct xec_pcr_config * const devcfg = dev->config; in disable_32k_crystal() local
434 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in disable_32k_crystal()
451 const struct xec_pcr_config * const devcfg = dev->config; in enable_32k_crystal() local
452 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in enable_32k_crystal()
477 hib_timer_delay(HIBTIMER_MS_TO_CNT(devcfg->xtal_enable_delay_ms)); in enable_32k_crystal()
492 const struct xec_pcr_config * const devcfg = dev->config; in check_32k_crystal() local
493 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base; in check_32k_crystal()
507 pcr->CNT32K_PER_MIN = devcfg->period_min; in check_32k_crystal()
508 pcr->CNT32K_PER_MAX = devcfg->period_max; in check_32k_crystal()
509 pcr->CNT32K_DV_MAX = devcfg->max_dc_va; in check_32k_crystal()
510 pcr->CNT32K_VALID_MIN = devcfg->min_valid; in check_32k_crystal()
563 const struct xec_pcr_config * const devcfg = dev->config; in connect_pll_32k() local
564 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base; in connect_pll_32k()
584 const struct xec_pcr_config * const devcfg = dev->config; in connect_periph_32k() local
585 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in connect_periph_32k()
609 const struct xec_pcr_config * const devcfg = dev->config; in get_pll_32k_source() local
610 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base; in get_pll_32k_source()
634 const struct xec_pcr_config * const devcfg = dev->config; in get_periph_32k_source() local
635 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in get_periph_32k_source()
672 const struct xec_pcr_config * const devcfg = dev->config; in soc_clk32_init() local
673 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base; in soc_clk32_init()
674 struct vbatr_hw_regs *const vbr = (struct vbatr_hw_regs *)devcfg->vbr_base; in soc_clk32_init()
702 if (!devcfg->clkmon_bypass) { in soc_clk32_init()
718 rc = pll_wait_lock_periph(pcr, devcfg->pll_lock_timeout_ms); in soc_clk32_init()
726 if (devcfg->dis_internal_osc) { in soc_clk32_init()
734 if (devcfg->dis_internal_osc) { in soc_clk32_init()
923 const struct xec_pcr_config * const devcfg = dev->config; in get_turbo_clock()
924 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base; in get_turbo_clock()
958 const struct xec_pcr_config * const devcfg = dev->config; in xec_clock_control_get_subsys_rate() local
959 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base; in xec_clock_control_get_subsys_rate()
1025 const struct xec_pcr_config * const devcfg = dev->config; in xec_clock_control_init() local
1026 struct pcr_hw_regs *const pcr = (struct pcr_hw_regs *)devcfg->pcr_base; in xec_clock_control_init()
1027 enum pll_clk32k_src pll_clk_src = devcfg->pll_src; in xec_clock_control_init()
1028 enum periph_clk32k_src periph_clk_src = devcfg->periph_src; in xec_clock_control_init()
1032 if (devcfg->xtal_se) { in xec_clock_control_init()
1038 rc = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in xec_clock_control_init()
1049 rc = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in xec_clock_control_init()
1059 xec_clock_control_core_clock_divider_set(devcfg->core_clk_div); in xec_clock_control_init()