Lines Matching refs:DEV_BASE
103 #define DEV_BASE(dev) ((DMAx_Type *)DEV_CFG(dev)->base) macro
140 #define EDMA_HW_TCD_SADDR(dev, ch) (DEV_BASE(dev)->TCD[ch].SADDR)
141 #define EDMA_HW_TCD_DADDR(dev, ch) (DEV_BASE(dev)->TCD[ch].DADDR)
142 #define EDMA_HW_TCD_BITER(dev, ch) (DEV_BASE(dev)->TCD[ch].BITER_ELINKNO)
143 #define EDMA_HW_TCD_CITER(dev, ch) (DEV_BASE(dev)->TCD[ch].CITER_ELINKNO)
144 #define EDMA_HW_TCD_CSR(dev, ch) (DEV_BASE(dev)->TCD[ch].CSR)
146 #define EDMA_HW_TCD_SADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_SADDR)
147 #define EDMA_HW_TCD_DADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_DADDR)
148 #define EDMA_HW_TCD_BITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_BITER_ELINKNO)
149 #define EDMA_HW_TCD_CITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_CITER_ELINKNO)
150 #define EDMA_HW_TCD_CSR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_CSR)
216 uint32_t flag = EDMA_GetChannelStatusFlags(DEV_BASE(dev), hw_channel); in dma_mcux_edma_irq_handler()
228 EDMA_ClearChannelStatusFlags(DEV_BASE(dev), channel, 0xFFFFFFFF); in dma_mcux_edma_irq_handler()
246 EDMA_GetErrorStatusFlags(DEV_BASE(dev))); in dma_mcux_edma_error_irq_handler()
248 EDMA_ClearChannelStatusFlags(DEV_BASE(dev), hw_channel, 0xFFFFFFFF); in dma_mcux_edma_error_irq_handler()
345 EDMA_TcdSetTransferConfigExt(DEV_BASE(dev), in dma_mcux_edma_configure_sg_loop()
350 EDMA_TcdEnableInterruptsExt(DEV_BASE(dev), in dma_mcux_edma_configure_sg_loop()
368 EDMA_TCD_SADDR(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) = in dma_mcux_edma_configure_sg_loop()
370 EDMA_TCD_DADDR(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) = in dma_mcux_edma_configure_sg_loop()
372 EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) = in dma_mcux_edma_configure_sg_loop()
374 EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) = in dma_mcux_edma_configure_sg_loop()
378 EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) |= in dma_mcux_edma_configure_sg_loop()
381 EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) &= in dma_mcux_edma_configure_sg_loop()
557 EDMA_ResetChannel(DEV_BASE(dev), hw_channel); in dma_mcux_edma_configure()
558 EDMA_CreateHandle(p_handle, DEV_BASE(dev), hw_channel); in dma_mcux_edma_configure()
563 EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, 0); in dma_mcux_edma_configure()
564 EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, slot); in dma_mcux_edma_configure()
568 EDMA_EnableChannelInterrupts(DEV_BASE(dev), hw_channel, kEDMA_ErrorInterruptEnable); in dma_mcux_edma_configure()
586 EDMA_SetChannelLink(DEV_BASE(dev), channel, kEDMA_MajorLink, in dma_mcux_edma_configure()
591 EDMA_SetChannelLink(DEV_BASE(dev), channel, kEDMA_MinorLink, in dma_mcux_edma_configure()
618 LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR); in dma_mcux_edma_start()
639 EDMA_ClearChannelStatusFlags(DEV_BASE(dev), hw_channel, in dma_mcux_edma_stop()
642 EDMA_ResetChannel(DEV_BASE(dev), hw_channel); in dma_mcux_edma_stop()
706 EDMA_TCD_SADDR(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) = EDMA_MMAP_ADDR(src); in edma_reload_loop()
707 EDMA_TCD_DADDR(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) = EDMA_MMAP_ADDR(dst); in edma_reload_loop()
708 EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) = size; in edma_reload_loop()
709 EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) = size; in edma_reload_loop()
711 EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) |= DMA_CSR_DREQ(1U); in edma_reload_loop()
712 sw_id = EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))); in edma_reload_loop()
719 EDMA_DisableChannelRequest(DEV_BASE(dev), channel); in edma_reload_loop()
743 EDMA_TCD_CSR(pre_tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) &= in edma_reload_loop()
751 EDMA_EnableAutoStopRequest(DEV_BASE(dev), channel, false); in edma_reload_loop()
761 EDMA_ClearChannelStatusFlags(DEV_BASE(dev), channel, kEDMA_DoneFlag); in edma_reload_loop()
767 EDMA_EnableChannelRequest(DEV_BASE(dev), channel); in edma_reload_loop()
848 EDMA_GetRemainingMajorLoopCount(DEV_BASE(dev), hw_channel) * in dma_mcux_edma_get_status()
859 LOG_DBG("DMA MP_CSR 0x%x", DEV_BASE(dev)->MP_CSR); in dma_mcux_edma_get_status()
860 LOG_DBG("DMA MP_ES 0x%x", DEV_BASE(dev)->MP_ES); in dma_mcux_edma_get_status()
861 LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_ES); in dma_mcux_edma_get_status()
862 LOG_DBG("DMA CHx_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_CSR); in dma_mcux_edma_get_status()
863 LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_ES); in dma_mcux_edma_get_status()
864 LOG_DBG("DMA CHx_INT 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_INT); in dma_mcux_edma_get_status()
865 LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].TCD_CSR); in dma_mcux_edma_get_status()
867 LOG_DBG("DMA MP_CSR 0x%x", DEV_BASE(dev)->MP_CSR); in dma_mcux_edma_get_status()
868 LOG_DBG("DMA MP_ES 0x%x", DEV_BASE(dev)->MP_ES); in dma_mcux_edma_get_status()
869 LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->TCD[hw_channel].CH_ES); in dma_mcux_edma_get_status()
870 LOG_DBG("DMA CHx_CSR 0x%x", DEV_BASE(dev)->TCD[hw_channel].CH_CSR); in dma_mcux_edma_get_status()
871 LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->TCD[hw_channel].CH_ES); in dma_mcux_edma_get_status()
872 LOG_DBG("DMA CHx_INT 0x%x", DEV_BASE(dev)->TCD[hw_channel].CH_INT); in dma_mcux_edma_get_status()
873 LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->TCD[hw_channel].CSR); in dma_mcux_edma_get_status()
875 LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR); in dma_mcux_edma_get_status()
876 LOG_DBG("DMA INT 0x%x", DEV_BASE(dev)->INT); in dma_mcux_edma_get_status()
877 LOG_DBG("DMA ERQ 0x%x", DEV_BASE(dev)->ERQ); in dma_mcux_edma_get_status()
878 LOG_DBG("DMA ES 0x%x", DEV_BASE(dev)->ES); in dma_mcux_edma_get_status()
879 LOG_DBG("DMA ERR 0x%x", DEV_BASE(dev)->ERR); in dma_mcux_edma_get_status()
880 LOG_DBG("DMA HRS 0x%x", DEV_BASE(dev)->HRS); in dma_mcux_edma_get_status()
881 LOG_DBG("data csr is 0x%x", DEV_BASE(dev)->TCD[hw_channel].CSR); in dma_mcux_edma_get_status()
928 EDMA_Init(DEV_BASE(dev), &userConfig); in dma_mcux_edma_init()
931 EDMA_EnableAllChannelLink(DEV_BASE(dev), true); in dma_mcux_edma_init()