Lines Matching refs:parent
1153 def parent(self) -> Optional['Node']: member in Node
1155 return self.edt._node2enode.get(self._node.parent) # type: ignore
1256 if not self.parent or not self.parent.parent:
1259 controller = self.parent.parent
1261 if controller.parent is None:
1263 return controller.parent
1305 if not self.parent or "gpio-controller" not in self.parent.props:
1308 if "#gpio-cells" not in self.parent._node.props:
1311 n_cells = self.parent._node.props["#gpio-cells"].to_num()
1316 controller = self.parent
1440 if not self.parent:
1443 pbinding = self.parent._binding
1457 if not self.parent:
1469 if self.parent.buses:
1471 return self.parent
1474 return self.parent.bus_node
2235 if not node.parent:
2655 parent: Optional[str],
2824 if not node.parent or "ranges" not in node.parent.props:
2828 if not node.parent.props["ranges"].value:
2835 return _translate(addr, node.parent)
2839 parent_address_cells = _address_cells(node.parent)
2845 for raw_range in _slice(node.parent, "ranges", 4*entry_cells,
2861 return _translate(parent_addr + addr - child_addr, node.parent)
2910 node = node.parent
2955 parent: dtlib_Node,
2962 if "interrupt-controller" in parent.props:
2963 return (parent, child_spec)
2981 parent, raw_spec = _map(
2982 "interrupt", child, parent, _raw_unit_addr(child, parent) + child_spec,
2986 return (parent, raw_spec[4*own_address_cells(parent):])
2991 parent: dtlib_Node,
3007 return _map(basename, child, parent, child_spec, spec_len_fn,
3014 parent: dtlib_Node,
3044 map_prop = parent.props.get(prefix + "-map")
3046 if require_controller and prefix + "-controller" not in parent.props:
3051 return (parent, child_spec)
3053 masked_child_spec = _mask(prefix, child, parent, child_spec)
3068 map_parent = parent.dt.phandle2node.get(phandle)
3082 prefix, child, parent, child_spec, parent_spec)
3085 return _map(prefix, parent, map_parent, parent_spec, spec_len_fn,
3095 parent: dtlib_Node,
3101 mask_prop = parent.props.get(prefix + "-map-mask")
3117 parent: dtlib_Node,
3129 pass_thru_prop = parent.props.get(prefix + "-map-pass-thru")
3146 def _raw_unit_addr(node: dtlib_Node, parent: dtlib_Node) -> bytes:
3150 iparent: Optional[dtlib_Node] = parent
3273 assert node.parent
3275 ret = _address_cells_self(node.parent)
3285 assert node.parent
3287 if "#size-cells" in node.parent.props:
3288 return node.parent.props["#size-cells"].to_num()