/*
 * Copyright (c) 2025 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/dt-bindings/pwm/pwm.h>

/ {
	aliases {
		i2s-node0 = &i2s0;
	};
};

&pinctrl {
	ssie0_default: ssie0_default {
		group1 {
			/* SSI_BCK SSI_LRCK SSI_TX SSI_RX */
			psels = <RA_PSEL(RA_PSEL_SSIE, 4, 3)>,
				<RA_PSEL(RA_PSEL_SSIE, 1, 13)>,
				<RA_PSEL(RA_PSEL_SSIE, 4, 5)>,
				<RA_PSEL(RA_PSEL_SSIE, 4, 6)>;
			drive-strength = "high";
		};
	};

	pwm2_default: pwm2_default {
		group1 {
			/* GTIOC2A */
			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 3)>;
		};
	};
};

&i2s0 {
	pinctrl-0 = <&ssie0_default>;
	pinctrl-names = "default";
	interrupts = <93 12>, <94 12>, <95 12>;
	interrupt-names = "ssi_txi", "ssi_rxi", "ssi_if";
	status = "okay";
	clocks = <&pclkb MSTPC 8>, <&ssi_internal_clock 0>;
	clock-names = "pclk", "audio-clock";
};

&pwm2 {
	pinctrl-0 = <&pwm2_default>;
	pinctrl-names = "default";
	interrupts = <91 12>, <92 12>;
	interrupt-names = "gtioca", "overflow";
	status = "okay";

	ssi_internal_clock: pwmclock {
		status = "okay";
		compatible = "pwm-clock";
		#clock-cells = <1>;
		pwms = <&pwm2 0 PWM_HZ(512000) PWM_POLARITY_NORMAL>;
	};
};