1# ARM64 core configuration options 2 3# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com> 4# SPDX-License-Identifier: Apache-2.0 5 6config CPU_CORTEX_A 7 bool 8 select CPU_CORTEX 9 select HAS_FLASH_LOAD_OFFSET 10 select SCHED_IPI_SUPPORTED if SMP 11 select CPU_HAS_FPU 12 select ARCH_HAS_SINGLE_THREAD_SUPPORT 13 select CPU_HAS_DCACHE 14 select CPU_HAS_ICACHE 15 imply FPU 16 imply FPU_SHARING 17 help 18 This option signifies the use of a CPU of the Cortex-A family. 19 20config CPU_AARCH64_CORTEX_R 21 bool 22 select CPU_CORTEX 23 select HAS_FLASH_LOAD_OFFSET 24 select CPU_HAS_DCACHE 25 select CPU_HAS_ICACHE 26 select ARCH_HAS_STACK_PROTECTION 27 select CPU_HAS_FPU 28 imply FPU 29 imply FPU_SHARING 30 help 31 This option signifies the use of a CPU of the Cortex-R 64-bit family. 32 33config CPU_CORTEX_A53 34 bool 35 select CPU_CORTEX_A 36 select ARMV8_A 37 help 38 This option signifies the use of a Cortex-A53 CPU 39 40config CPU_CORTEX_A55 41 bool 42 select CPU_CORTEX_A 43 select ARMV8_A 44 help 45 This option signifies the use of a Cortex-A55 CPU 46 47config CPU_CORTEX_A57 48 bool 49 select CPU_CORTEX_A 50 select ARMV8_A 51 help 52 This option signifies the use of a Cortex-A57 CPU 53 54config CPU_CORTEX_A72 55 bool 56 select CPU_CORTEX_A 57 select ARMV8_A 58 help 59 This option signifies the use of a Cortex-A72 CPU 60 61config CPU_CORTEX_A76 62 bool 63 select CPU_CORTEX_A 64 select ARMV8_A 65 help 66 This option signifies the use of a Cortex-A76 CPU 67 68config CPU_CORTEX_A76_A55 69 bool 70 select CPU_CORTEX_A 71 select ARMV8_A 72 help 73 This option signifies the use of a Cortex-A76 and A55 big little CPU cluster 74 75config CPU_CORTEX_R82 76 bool 77 select CPU_AARCH64_CORTEX_R 78 select ARMV8_R 79 help 80 This option signifies the use of a Cortex-R82 CPU 81 82config HAS_ARM_SMCCC 83 bool 84 help 85 Include support for the Secure Monitor Call (SMC) and Hypervisor 86 Call (HVC) instructions on Armv7 and above architectures. 87 88config NUM_IRQS 89 int 90 91config MAIN_STACK_SIZE 92 default 4096 93 94config IDLE_STACK_SIZE 95 default 4096 96 97config ISR_STACK_SIZE 98 default 4096 99 100config TEST_EXTRA_STACK_SIZE 101 default 2048 102 103config SYSTEM_WORKQUEUE_STACK_SIZE 104 default 4096 105 106config CMSIS_THREAD_MAX_STACK_SIZE 107 default 4096 108 109config CMSIS_V2_THREAD_MAX_STACK_SIZE 110 default 4096 111 112config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE 113 default 4096 114 115config IPM_CONSOLE_STACK_SIZE 116 default 2048 117 118config AARCH64_IMAGE_HEADER 119 bool "Add image header" 120 default y if ARM_MMU || ARM_MPU 121 help 122 This option enables standard ARM64 boot image header used by Linux 123 and understood by loaders such as u-boot on Xen xl tool. 124 125config PRIVILEGED_STACK_SIZE 126 default 4096 127 128config KOBJECT_TEXT_AREA 129 default 1024 if UBSAN 130 default 512 if TEST 131 132config WAIT_AT_RESET_VECTOR 133 bool "Wait at reset vector" 134 default n 135 help 136 Spin at reset vector waiting for debugger to attach and resume 137 execution 138 139config ARM64_SAFE_EXCEPTION_STACK 140 bool "To enable the safe exception stack" 141 help 142 The safe exception stack is used for checking whether the kernel stack 143 overflows during the exception happens from EL1. This stack is not 144 used for user stack overflow checking, because kernel stack support 145 the checking work. 146 147config ARM64_EXCEPTION_STACK_TRACE 148 bool 149 default y 150 depends on FRAME_POINTER 151 help 152 Internal config to enable runtime stack traces on fatal exceptions. 153 154config ARCH_HAS_STACKWALK 155 bool 156 default y 157 depends on FRAME_POINTER 158 help 159 Internal config to indicate that the arch_stack_walk() API is implemented 160 and it can be enabled. 161 162config ARM64_SAFE_EXCEPTION_STACK_SIZE 163 int "The stack size of the safe exception stack" 164 default 4096 165 depends on ARM64_SAFE_EXCEPTION_STACK 166 help 167 The stack size of the safe exception stack. The safe exception stack 168 requires to be enough to do the stack overflow check. 169 170config ARM64_FALLBACK_ON_RESERVED_CORES 171 bool "To enable fallback on reserved cores" 172 help 173 Give the ability to define more cores in the device tree than required 174 via CONFIG_MP_MAX_NUM_CPUS. The extra cores in the device tree 175 become reserved. If there is an issue powering on a core during boot 176 then that core will be skipped and the next core in the device tree 177 will be used. 178 179config ARM64_STACK_PROTECTION 180 bool 181 default y if HW_STACK_PROTECTION 182 depends on ARM_MPU 183 select THREAD_STACK_INFO 184 select ARM64_SAFE_EXCEPTION_STACK 185 help 186 This option leverages the MMU or MPU to cause a system fatal error if 187 the bounds of the current process stack are overflowed. This is done 188 by preceding all stack areas with a fixed guard region. 189 190if CPU_CORTEX_A 191 192config ARMV8_A_NS 193 bool "ARMv8-A Normal World (Non-Secure world of Trustzone)" 194 help 195 This option signifies that Zephyr is entered in TrustZone 196 Non-Secure state 197 198config ARMV8_A 199 bool 200 select ATOMIC_OPERATIONS_BUILTIN 201 select CPU_HAS_MMU 202 select ARCH_HAS_USERSPACE if ARM_MMU 203 select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MMU 204 help 205 This option signifies the use of an ARMv8-A processor 206 implementation. 207 208 From https://developer.arm.com/products/architecture/cpu-architecture/a-profile: 209 The Armv8-A architecture introduces the ability to use 64-bit and 210 32-bit Execution states, known as AArch64 and AArch32 respectively. 211 The AArch64 Execution state supports the A64 instruction set, holds 212 addresses in 64-bit registers and allows instructions in the base 213 instruction set to use 64-bit registers for their processing. The AArch32 214 Execution state is a 32-bit Execution state that preserves backwards 215 compatibility with the Armv7-A architecture and enhances that profile 216 so that it can support some features included in the AArch64 state. 217 It supports the T32 and A32 instruction sets. 218 219rsource "xen/Kconfig" 220 221endif # CPU_CORTEX_A 222 223if CPU_AARCH64_CORTEX_R 224 225config ARMV8_R 226 bool 227 select ATOMIC_OPERATIONS_BUILTIN 228 select SCHED_IPI_SUPPORTED if SMP 229 select ARCH_HAS_USERSPACE if ARM_MPU 230 help 231 This option signifies the use of an ARMv8-R processor 232 implementation. 233 234 From https://developer.arm.com/products/architecture/cpu-architecture/r-profile: 235 The Armv8-R architecture targets at the Real-time profile. It introduces 236 virtualization at the highest security level while retaining the 237 Protected Memory System Architecture (PMSA) based on a Memory Protection 238 Unit (MPU). It supports the A32 and T32 instruction sets. 239 240rsource "cortex_r/Kconfig" 241 242endif # CPU_AARCH64_CORTEX_R 243 244if CPU_CORTEX_A || CPU_AARCH64_CORTEX_R 245 246config GEN_ISR_TABLES 247 default y 248 249config GEN_IRQ_VECTOR_TABLE 250 default n 251 252config ARM_MMU 253 bool "ARM MMU Support" 254 default n if CPU_AARCH64_CORTEX_R 255 default y 256 select MMU 257 select SRAM_REGION_PERMISSIONS 258 select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE 259 select ARCH_MEM_DOMAIN_DATA if USERSPACE 260 help 261 Memory Management Unit support. 262 263config XIP 264 select AARCH64_IMAGE_HEADER 265 266config ARM64_SET_VMPIDR_EL2 267 bool "Set VMPIDR_EL2 at EL2 stage" 268 help 269 VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. 270 This is the value returned by EL1 reads of MPIDR_EL1. 271 This register may already be set by bootloader at the EL2 stage, if 272 not, Zephyr should set it. 273 274if ARM_MMU 275 276config MMU_PAGE_SIZE 277 default 0x1000 278 279choice ARM64_VA_BITS 280 prompt "Virtual address space size" 281 default ARM64_VA_BITS_32 282 help 283 Allows choosing one of multiple possible virtual address 284 space sizes. The level of translation table is determined by 285 a combination of page size and virtual address space size. 286 287config ARM64_VA_BITS_32 288 bool "32-bit" 289 290config ARM64_VA_BITS_36 291 bool "36-bit" 292 293config ARM64_VA_BITS_40 294 bool "40-bit" 295 296config ARM64_VA_BITS_42 297 bool "42-bit" 298 299config ARM64_VA_BITS_48 300 bool "48-bit" 301endchoice 302 303config ARM64_VA_BITS 304 int 305 default 32 if ARM64_VA_BITS_32 306 default 36 if ARM64_VA_BITS_36 307 default 40 if ARM64_VA_BITS_40 308 default 42 if ARM64_VA_BITS_42 309 default 48 if ARM64_VA_BITS_48 310 311choice ARM64_PA_BITS 312 prompt "Physical address space size" 313 default ARM64_PA_BITS_32 314 help 315 Choose the maximum physical address range that the kernel will 316 support. 317 318config ARM64_PA_BITS_32 319 bool "32-bit" 320 321config ARM64_PA_BITS_36 322 bool "36-bit" 323 324config ARM64_PA_BITS_40 325 bool "40-bit" 326 327config ARM64_PA_BITS_42 328 bool "42-bit" 329 330config ARM64_PA_BITS_48 331 bool "48-bit" 332endchoice 333 334config ARM64_PA_BITS 335 int 336 default 32 if ARM64_PA_BITS_32 337 default 36 if ARM64_PA_BITS_36 338 default 40 if ARM64_PA_BITS_40 339 default 42 if ARM64_PA_BITS_42 340 default 48 if ARM64_PA_BITS_48 341 342config MAX_XLAT_TABLES 343 int "Maximum numbers of translation tables" 344 default 20 if USERSPACE && (ARM64_VA_BITS >= 40) 345 default 16 if USERSPACE 346 default 12 if (ARM64_VA_BITS >= 40) 347 default 8 348 help 349 This option specifies the maximum numbers of translation tables. 350 Based on this, translation tables are allocated at compile time and 351 used at runtime as needed. If the runtime need exceeds preallocated 352 numbers of translation tables, it will result in assert. Number of 353 translation tables required is decided based on how many discrete 354 memory regions (both normal and device memory) are present on given 355 platform and how much granularity is required while assigning 356 attributes to these memory regions. 357 358endif # ARM_MMU 359 360config ARM64_DCACHE_ALL_OPS 361 bool "Provide data cache APIs to operate all data caches" 362 depends on CACHE_MANAGEMENT && DCACHE 363 help 364 Enable this option to provide the data cache APIs to flush or 365 invalidate all data caches. 366 367config ARM64_BOOT_DISABLE_DCACHE 368 bool "Disable data cache before enable MMU when booting from EL2" 369 depends on ARM64_DCACHE_ALL_OPS 370 help 371 To make it safe, if data cache is enabled in case of Zephyr is booting 372 from EL2, enable this option, it will clean and invalidate all data 373 cache and then disable data cache, it will will be re-enabled after 374 MMU is configured and enabled. 375 376endif # CPU_CORTEX_A || CPU_AARCH64_CORTEX_R 377