1# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com> 2# SPDX-License-Identifier: Apache-2.0 3 4config RISCV_ISA_RV32I 5 bool 6 help 7 RV32I Base Integer Instruction Set - 32bit 8 9config RISCV_ISA_RV32E 10 bool 11 help 12 RV32E Base Integer Instruction Set (Embedded) - 32bit 13 14config RISCV_ISA_RV64I 15 bool 16 default y if 64BIT 17 help 18 RV64I Base Integer Instruction Set - 64bit 19 20config RISCV_ISA_RV128I 21 bool 22 help 23 RV128I Base Integer Instruction Set - 128bit 24 25config RISCV_ISA_EXT_M 26 bool 27 help 28 (M) - Standard Extension for Integer Multiplication and Division 29 30 Standard integer multiplication and division instruction extension, 31 which is named "M" and contains instructions that multiply or divide 32 values held in two integer registers. 33 34config RISCV_ISA_EXT_A 35 bool 36 imply RISCV_ISA_EXT_ZAAMO 37 imply RISCV_ISA_EXT_ZALRSC 38 help 39 (A) - Standard Extension for Atomic Instructions 40 41 The standard atomic instruction extension is denoted by instruction 42 subset name "A", and contains instructions that atomically 43 read-modify-write memory to support synchronization between multiple 44 RISC-V threads running in the same memory space. 45 46config RISCV_ISA_EXT_F 47 bool 48 help 49 (F) - Standard Extension for Single-Precision Floating-Point 50 51 Standard instruction-set extension for single-precision 52 floating-point, which is named "F" and adds single-precision 53 floating-point computational instructions compliant with the IEEE 54 754-2008 arithmetic standard. 55 56config RISCV_ISA_EXT_D 57 bool 58 depends on RISCV_ISA_EXT_F 59 help 60 (D) - Standard Extension for Double-Precision Floating-Point 61 62 Standard double-precision floating-point instruction-set extension, 63 which is named "D" and adds double-precision floating-point 64 computational instructions compliant with the IEEE 754-2008 65 arithmetic standard. 66 67config RISCV_ISA_EXT_G 68 bool 69 select RISCV_ISA_EXT_M 70 select RISCV_ISA_EXT_A 71 select RISCV_ISA_EXT_F 72 select RISCV_ISA_EXT_D 73 select RISCV_ISA_EXT_ZICSR 74 select RISCV_ISA_EXT_ZIFENCEI 75 help 76 (IMAFDZicsr_Zifencei) IMAFDZicsr_Zifencei extensions 77 78config RISCV_ISA_EXT_Q 79 bool 80 depends on RISCV_ISA_RV64I 81 depends on RISCV_ISA_EXT_F 82 depends on RISCV_ISA_EXT_D 83 help 84 (Q) - Standard Extension for Quad-Precision Floating-Point 85 86 Standard extension for 128-bit binary floating-point instructions 87 compliant with the IEEE 754-2008 arithmetic standard. The 128-bit or 88 quad-precision binary floatingpoint instruction subset is named "Q". 89 90config RISCV_ISA_EXT_C 91 bool 92 select RISCV_ISA_EXT_ZCA 93 select RISCV_ISA_EXT_ZCD if RISCV_ISA_EXT_D 94 select RISCV_ISA_EXT_ZCF if RISCV_ISA_EXT_F && (RISCV_ISA_RV32I || RISCV_ISA_RV32E) 95 help 96 (C) - Standard Extension for Compressed Instructions 97 98 RISC-V standard compressed instruction set extension, named "C", 99 which reduces static and dynamic code size by adding short 16-bit 100 instruction encodings for common operations. 101 102config RISCV_ISA_EXT_ZICNTR 103 bool 104 depends on RISCV_ISA_EXT_ZICSR 105 help 106 (Zicntr) - Standard Extension for Base Counters and Timers 107 108 The Zicntr standard extension comprises the three counters (CYCLE, TIME, and INSTRET), 109 which have dedicated functions (cycle count, real-time clock and instructions retired, 110 respectively). 111 112config RISCV_ISA_EXT_ZICSR 113 bool 114 help 115 (Zicsr) - Standard Extension for Control and Status Register (CSR) Instructions 116 117 The "Zicsr" extension introduces support for the full set of CSR 118 instructions that operate on CSRs registers. 119 120config RISCV_ISA_EXT_ZIFENCEI 121 bool 122 help 123 (Zifencei) - Standard Extension for Instruction-Fetch Fence 124 125 The "Zifencei" extension includes the FENCE.I instruction that 126 provides explicit synchronization between writes to instruction 127 memory and instruction fetches on the same hart. 128 129config RISCV_ISA_EXT_ZAAMO 130 bool 131 help 132 (Zaamo) - Atomic memory operation subset of the A extension 133 134 The Zaamo extension enables support for AMO*.W/D-style instructions. 135 136config RISCV_ISA_EXT_ZALRSC 137 bool 138 help 139 (Zalrsc) - Load-Reserved/Store-Conditional subset of the A extension 140 141 The Zalrsc extension enables support for LR.W/D and SC.W/D-style instructions. 142 143config RISCV_ISA_EXT_ZCA 144 bool 145 help 146 (Zca) - Zba Extension for Compressed Instructions 147 148 The Zca extension is a subset of the C extension that does not include 149 the floating-point load and store instructions. 150 151config RISCV_ISA_EXT_ZCB 152 bool 153 depends on RISCV_ISA_EXT_ZCA 154 help 155 (Zcb) - Zcb Extension for Simple Compressed Instructions 156 157 The Zcb extension is a set of simple code-size saving instructions 158 which are easy to implement on all CPUs. 159 160config RISCV_ISA_EXT_ZCD 161 bool 162 depends on RISCV_ISA_EXT_D 163 depends on RISCV_ISA_EXT_ZCA 164 help 165 (Zcd) - Zcd Extension for Double-Precision FP Compressed Instructions 166 167 The Zcd extension consists of compressed double-precision 168 floating-point load and store instructions. 169 170config RISCV_ISA_EXT_ZCF 171 bool 172 depends on RISCV_ISA_RV32I || RISCV_ISA_RV32E 173 depends on RISCV_ISA_EXT_F 174 depends on RISCV_ISA_EXT_ZCA 175 help 176 (Zcf) - Zcf Extension for Single-Precision FP Compressed Instructions 177 178 The Zcf extension consists of compressed single-precision 179 floating-point load and store instructions. 180 181config RISCV_ISA_EXT_ZCMP 182 bool 183 depends on RISCV_ISA_EXT_ZCA 184 depends on !RISCV_ISA_EXT_ZCD 185 help 186 (Zcmp) - Zcmp Extension for Complex Compressed Instructions 187 188 The Zcmp extension consists of complex operations intended for 189 embedded CPUs. 190 191config RISCV_ISA_EXT_ZCMT 192 bool 193 depends on RISCV_ISA_EXT_ZICSR 194 depends on RISCV_ISA_EXT_ZCA 195 depends on !RISCV_ISA_EXT_ZCD 196 help 197 (Zcmt) - Zcmt Extension for Compressed Table Jump Instructions 198 199 The Zcmt extension consists of compressed table jump instructions for 200 embedded CPUs. 201 202config RISCV_ISA_EXT_ZBA 203 bool 204 help 205 (Zba) - Zba BitManip Extension 206 207 The Zba instructions can be used to accelerate the generation of 208 addresses that index into arrays of basic types (halfword, word, 209 doubleword) using both unsigned word-sized and XLEN-sized indices: a 210 shifted index is added to a base address. 211 212config RISCV_ISA_EXT_ZBB 213 bool 214 help 215 (Zbb) - Zbb BitManip Extension (Basic bit-manipulation) 216 217 The Zbb instructions can be used for basic bit-manipulation (logical 218 with negate, count leading / trailing zero bits, count population, 219 etc...). 220 221config RISCV_ISA_EXT_ZBC 222 bool 223 help 224 (Zbc) - Zbc BitManip Extension (Carry-less multiplication) 225 226 The Zbc instructions can be used for carry-less multiplication that 227 is the multiplication in the polynomial ring over GF(2). 228 229config RISCV_ISA_EXT_ZBS 230 bool 231 help 232 (Zbs) - Zbs BitManip Extension (Single-bit instructions) 233 234 The Zbs instructions can be used for single-bit instructions that 235 provide a mechanism to set, clear, invert, or extract a single bit in 236 a register. 237 238config RISCV_ISA_EXT_ZMMUL 239 bool 240 help 241 (Zmmul) - Zmmul Extension for Integer Multiplication 242 243 The Zmmul extension implements the multiplication subset of the M 244 extension. 245