1 /* 2 * Copyright (c) 2021-2024 Nordic Semiconductor ASA 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #if (EVENT_TIMER_ID == 0) 8 9 /* PPI channel 20 is pre-programmed with the following fixed settings: 10 * EEP: TIMER0->EVENTS_COMPARE[0] 11 * TEP: RADIO->TASKS_TXEN 12 */ 13 #define HAL_RADIO_ENABLE_TX_ON_TICK_PPI 20 14 /* PPI channel 21 is pre-programmed with the following fixed settings: 15 * EEP: TIMER0->EVENTS_COMPARE[0] 16 * TEP: RADIO->TASKS_RXEN 17 */ 18 #define HAL_RADIO_ENABLE_RX_ON_TICK_PPI 21 19 20 /* PPI channel 26 is pre-programmed with the following fixed settings: 21 * EEP: RADIO->EVENTS_ADDRESS 22 * TEP: TIMER0->TASKS_CAPTURE[1] 23 */ 24 #define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 26 25 26 /* PPI channel 22 is pre-programmed with the following fixed settings: 27 * EEP: TIMER0->EVENTS_COMPARE[1] 28 * TEP: RADIO->TASKS_DISABLE 29 */ 30 #define HAL_RADIO_DISABLE_ON_HCTO_PPI 22 31 32 /* PPI channel 27 is pre-programmed with the following fixed settings: 33 * EEP: RADIO->EVENTS_END 34 * TEP: TIMER0->TASKS_CAPTURE[2] 35 */ 36 #define HAL_RADIO_END_TIME_CAPTURE_PPI 27 37 38 #else /* EVENT_TIMER_ID != 0 */ 39 40 #define HAL_RADIO_ENABLE_TX_ON_TICK_PPI 2 41 #define HAL_RADIO_ENABLE_RX_ON_TICK_PPI 2 42 #define HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI 3 43 #define HAL_RADIO_DISABLE_ON_HCTO_PPI 4 44 #define HAL_RADIO_END_TIME_CAPTURE_PPI 5 45 46 #endif /* EVENT_TIMER_ID != 0 */ 47 48 /* Start event timer on RTC tick wire the RTC0 EVENTS_COMPARE[2] event to 49 * EVENT_TIMER TASKS_START task. 50 */ 51 #define HAL_EVENT_TIMER_START_PPI 6 52 53 /* Capture event timer on Radio ready, wire the RADIO EVENTS_READY event to the 54 * EVENT_TIMER TASKS_CAPTURE[<radio ready timer>] task. 55 */ 56 #define HAL_RADIO_READY_TIME_CAPTURE_PPI 7 57 58 /* Trigger encryption task upon address reception: 59 * wire the RADIO EVENTS_ADDRESS event to the CCM TASKS_CRYPT task. 60 * 61 * PPI channel 25 is pre-programmed with the following fixed settings: 62 * EEP: RADIO->EVENTS_ADDRESS 63 * TEP: CCM->TASKS_CRYPT 64 */ 65 #define HAL_TRIGGER_CRYPT_PPI 25 66 67 /* Trigger automatic address resolution on Bit counter match: 68 * wire the RADIO EVENTS_BCMATCH event to the AAR TASKS_START task. 69 * 70 * PPI channel 23 is pre-programmed with the following fixed settings: 71 * EEP: RADIO->EVENTS_BCMATCH 72 * TEP: AAR->TASKS_START 73 */ 74 #define HAL_TRIGGER_AAR_PPI 23 75 76 /* Trigger Radio Rate override upon Rateboost event. */ 77 #if defined(CONFIG_BT_CTLR_PHY_CODED) && \ 78 defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED) 79 #define HAL_TRIGGER_RATEOVERRIDE_PPI 14 80 #endif /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */ 81 82 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN) || defined(HAL_RADIO_GPIO_HAVE_LNA_PIN) 83 #define HAL_ENABLE_PALNA_PPI 15 84 #define HAL_DISABLE_PALNA_PPI 16 85 #endif /* HAL_RADIO_GPIO_HAVE_PA_PIN || HAL_RADIO_GPIO_HAVE_LNA_PIN */ 86 87 #if defined(HAL_RADIO_FEM_IS_NRF21540) 88 #define HAL_ENABLE_FEM_PPI 4 89 #define HAL_DISABLE_FEM_PPI 5 90 #endif /* HAL_RADIO_FEM_IS_NRF21540 */ 91 92 #if !defined(CONFIG_BT_CTLR_TIFS_HW) 93 /* PPI setup used for SW-based auto-switching during TIFS. */ 94 95 #if (EVENT_TIMER_ID == 0) 96 97 /* Clear SW-switch timer on packet end: 98 * wire the RADIO EVENTS_END event to SW_SWITCH_TIMER TASKS_CLEAR task. 99 * 100 * Note: this PPI is not needed if we use a single TIMER instance in radio.c 101 */ 102 #define HAL_SW_SWITCH_TIMER_CLEAR_PPI 8 103 104 #else /* EVENT_TIMER_ID != 0 */ 105 106 /* Clear event timer (sw-switch timer) on Radio end: 107 * wire the RADIO EVENTS_END event to the 108 * EVENT_TIMER TASKS_CLEAR task. 109 * 110 * Note: in nRF52X this PPI channel is forked for both capturing and clearing 111 * timer on RADIO EVENTS_END. 112 */ 113 #define HAL_SW_SWITCH_TIMER_CLEAR_PPI HAL_RADIO_END_TIME_CAPTURE_PPI 114 115 #endif /* EVENT_TIMER_ID != 0 */ 116 117 /* Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event 118 * to a PPI GROUP TASK DISABLE task (PPI group with index <index>). 119 * 2 adjacent PPIs (9 & 10) and 2 adjacent PPI groups are used for this wiring; 120 * <index> must be 0 or 1. <offset> must be a valid TIMER CC register offset. 121 */ 122 #if defined(CONFIG_SOC_NRF52805) 123 #define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE 2 124 #else /* CONFIG_SOC_NRF52805 */ 125 #define HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_BASE 9 126 #endif 127 128 /* Wire the RADIO EVENTS_END event to one of the PPI GROUP TASK ENABLE task. 129 * 2 adjacent PPI groups are used for this wiring. 'index' must be 0 or 1. 130 */ 131 #if defined(CONFIG_SOC_NRF52805) 132 #define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI 9 133 #else /* CONFIG_SOC_NRF52805 */ 134 #define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI 11 135 #endif 136 137 /*Enable Radio at specific time-stamp: 138 * wire the SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event 139 * to RADIO TASKS_TXEN/RXEN task. 140 * 2 adjacent PPIs (12 & 13) are used for this wiring; <index> must be 0 or 1. 141 * <offset> must be a valid TIMER CC register offset. 142 */ 143 #if defined(CONFIG_SOC_NRF52805) 144 #define HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE 4 145 #else /* CONFIG_SOC_NRF52805 */ 146 #define HAL_SW_SWITCH_RADIO_ENABLE_PPI_BASE 12 147 #endif 148 149 #if defined(CONFIG_BT_CTLR_PHY_CODED) && \ 150 defined(CONFIG_HAS_HW_NRF_RADIO_BLE_CODED) 151 152 /* Wire the SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event 153 * to RADIO TASKS_TXEN/RXEN task. 154 */ 155 #define HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE 17 156 157 /* Cancel the SW switch timer running considering S8 timing: 158 * wire the RADIO EVENTS_RATEBOOST event to SW_SWITCH_TIMER TASKS_CAPTURE task. 159 */ 160 #define HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI 19 161 162 #endif /* CONFIG_BT_CTLR_PHY_CODED && CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */ 163 164 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE) 165 /* Wire the SW SWITCH PHYEND delay compensation TIMER EVENTS_COMPARE[<cc_offset>] event to software 166 * switch TIMER0->CLEAR task. 167 * 168 * Note: Use the same number of PPIs as for PHY CODED HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE. 169 * The CTE is not allowed in PDUs sent over PHY CODED so this PPI may be re-used. 170 */ 171 #define HAL_SW_SWITCH_RADIO_ENABLE_PHYEND_DELAY_COMPENSATION_PPI_BASE 17 172 173 /* Cancel the SW switch timer running considering PHYEND delay compensation timing: 174 * wire the RADIO EVENTS_CTEPRESENT event to SW_SWITCH_TIMER TASKS_CAPTURE task. 175 * 176 * Note: Use the same number of PPIs as for PHY CODED: HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI. 177 * The CTE is not allowed in PDUs sent over PHY CODED so this PPI may be re-used. 178 */ 179 #define HAL_SW_SWITCH_TIMER_PHYEND_DELAY_COMPENSATION_DISABLE_PPI 19 180 #endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */ 181 182 #if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX) 183 /* Trigger encryption task upon bit counter match event fire: 184 * wire the RADIO EVENTS_BCMATCH event to the CCM TASKS_CRYPT task. 185 * 186 * Note: The PPI number is shared with HAL_TRIGGER_RATEOVERRIDE_PPI because it is used only 187 * when direction finding RX and PHY is set to PHY1M. Due to that it can be shared with Radio Rate 188 * override. 189 */ 190 #define HAL_TRIGGER_CRYPT_DELAY_PPI 14 191 #endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */ 192 193 /* The 2 adjacent PPI groups used for implementing SW_SWITCH_TIMER-based 194 * auto-switch for TIFS. 'index' must be 0 or 1. 195 */ 196 #define SW_SWITCH_TIMER_TASK_GROUP_BASE 0 197 #define SW_SWITCH_SINGLE_TIMER_TASK_GROUP_IDX 2 198 #endif /* !CONFIG_BT_CTLR_TIFS_HW */ 199