1/*
2 * Copyright (c) 2025 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/n6/stm32n657X0.dtsi>
8#include <st/n6/stm32n657x0hxq-pinctrl.dtsi>
9#include "zephyr/dt-bindings/display/panel.h"
10#include <zephyr/dt-bindings/flash_controller/xspi.h>
11#include <zephyr/dt-bindings/gpio/raspberrypi-csi-connector.h>
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13#include <zephyr/dt-bindings/video/video-interfaces.h>
14#include "arduino_r3_connector.dtsi"
15
16/ {
17	chosen {
18		zephyr,console = &usart1;
19		zephyr,shell-uart = &usart1;
20		zephyr,sram = &axisram2;
21		zephyr,canbus = &fdcan1;
22		zephyr,display = &ltdc;
23		zephyr,touch = &gt911;
24		spi-flash0 = &mx66uw1g45g;
25		zephyr,flash-controller = &mx66uw1g45g;
26		zephyr,flash = &mx66uw1g45g;
27		zephyr,code-partition = &slot0_partition;
28	};
29
30	aliases {
31		led0 = &green_led_1;
32	};
33
34	lvgl_pointer {
35		compatible = "zephyr,lvgl-pointer-input";
36		input = <&gt911>;
37		display = <&ltdc>;
38		invert-y;
39	};
40
41	psram: memory@90000000 {
42		compatible = "zephyr,memory-region";
43		reg = <0x90000000 DT_SIZE_M(32)>;
44		zephyr,memory-region = "PSRAM";
45		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
46	};
47
48	leds: leds {
49		compatible = "gpio-leds";
50
51		green_led_1: led_1 {
52			gpios = <&gpioo 1 GPIO_ACTIVE_HIGH>;
53			label = "User LD1";
54		};
55
56		red_led_1: led_2 {
57			gpios = <&gpiog 10 GPIO_ACTIVE_HIGH>;
58			label = "User LD2";
59		};
60	};
61
62	csi_connector: connector_csi {
63		compatible = "raspberrypi,csi-connector";
64		#gpio-cells = <2>;
65		gpio-map-mask = <0xffffffff 0xffffffc0>;
66		gpio-map-pass-thru = <0 0x3f>;
67		gpio-map = <CSI_IO0  0 &gpioc 8  0>,
68			   <CSI_IO1  0 &gpiod 2  0>;
69	};
70};
71
72&i2c2 {
73	status = "okay";
74	clocks = <&rcc STM32_CLOCK(APB1, 22)>,
75		 <&rcc STM32_SRC_CKPER I2C2_SEL(1)>;
76	pinctrl-0 = <&i2c2_scl_pd14 &i2c2_sda_pd4>;
77	pinctrl-names = "default";
78	clock-frequency = <I2C_BITRATE_FAST>;
79
80	gt911: gt911@5d {
81		compatible = "goodix,gt911";
82		reg = <0x5d>;
83		reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
84		irq-gpios = <&gpioq 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
85	};
86};
87
88&clk_hse {
89	hse-div2;
90	clock-frequency = <DT_FREQ_M(48)>;
91	status = "okay";
92};
93
94&clk_hsi {
95	hsi-div = <1>;
96	status = "okay";
97};
98
99&pll1 {
100	clocks = <&clk_hse>;
101	div-m = <3>;
102	mul-n = <150>;
103	div-p1 = <1>;
104	div-p2 = <1>;
105	status = "okay";
106};
107
108&pll2 {
109	clocks = <&clk_hsi>;
110	div-m = <2>;
111	mul-n = <48>;
112	div-p1 = <1>;
113	div-p2 = <1>;
114	status = "okay";
115};
116
117&pll3 {
118	clocks = <&clk_hse>;
119	div-m = <3>;
120	mul-n = <125>;
121	div-p1 = <1>;
122	div-p2 = <1>;
123	status = "okay";
124};
125
126&pll4 {
127	clocks = <&clk_hsi>;
128	div-m = <4>;
129	mul-n = <75>;
130	div-p1 = <1>;
131	div-p2 = <1>;
132	status = "okay";
133};
134
135&ic1 {
136	pll-src = <1>;
137	ic-div = <3>;
138	status = "okay";
139};
140
141&ic2 {
142	pll-src = <1>;
143	ic-div = <6>;
144	status = "okay";
145};
146
147&ic3 {
148	pll-src = <1>;
149	ic-div = <6>;
150	status = "okay";
151};
152
153&ic4 {
154	pll-src = <2>;
155	ic-div = <32>;
156	status = "okay";
157};
158
159&ic6 {
160	pll-src = <3>;
161	ic-div = <2>;
162	status = "okay";
163};
164
165&ic11 {
166	pll-src = <1>;
167	ic-div = <3>;
168	status = "okay";
169};
170
171&ic16 {
172	pll-src = <4>;
173	ic-div = <60>;
174	status = "okay";
175};
176
177&ic17 {
178	pll-src = <1>;
179	ic-div = <4>;
180	status = "okay";
181};
182
183&ic18 {
184	pll-src = <1>;
185	ic-div = <60>;
186	status = "okay";
187};
188
189&perck {
190	clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
191	status = "okay";
192};
193
194&cpusw {
195	clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
196	clock-frequency = <DT_FREQ_M(800)>;
197	status = "okay";
198};
199
200&rcc {
201	/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
202	clocks = <&ic2>;
203	clock-frequency = <DT_FREQ_M(400)>;
204	ahb-prescaler = <2>;
205	timg-prescaler = <2>;
206};
207
208&adc1 {
209	clocks = <&rcc STM32_CLOCK(AHB1, 5)>,
210		 <&rcc STM32_SRC_CKPER ADC12_SEL(1)>;
211	pinctrl-0 = <&adc1_inp10_pa9 &adc1_inp11_pa10>; /* Arduino A1 & A2 */
212	pinctrl-names = "default";
213	vref-mv = <1800>;
214	status = "okay";
215};
216
217&fdcan1 {
218	clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
219		 <&rcc STM32_SRC_CKPER FDCAN_SEL(1)>;
220	pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_ph2>;
221	pinctrl-names = "default";
222	status = "okay";
223};
224
225csi_i2c: &i2c1 {
226	clocks = <&rcc STM32_CLOCK(APB1, 21)>,
227		 <&rcc STM32_SRC_CKPER I2C1_SEL(1)>;
228	pinctrl-0 = <&i2c1_scl_ph9 &i2c1_sda_pc1>;
229	pinctrl-names = "default";
230	clock-frequency = <I2C_BITRATE_STANDARD>;
231	status = "okay";
232};
233
234&i2c4 {
235	clocks = <&rcc STM32_CLOCK(APB4, 7)>,
236		 <&rcc STM32_SRC_CKPER I2C4_SEL(1)>;
237	pinctrl-0 = <&i2c4_scl_pe13 &i2c4_sda_pe14>;
238	pinctrl-names = "default";
239	clock-frequency = <I2C_BITRATE_STANDARD>;
240	status = "okay";
241};
242
243&sdmmc2 {
244	status = "okay";
245	clocks = <&rcc STM32_CLOCK(AHB5, 7)>,
246		 <&rcc STM32_SRC_IC4 SDMMC2_SEL(2)>;
247	pinctrl-0 = <&sdmmc2_d0_pc4 &sdmmc2_d1_pc5
248			&sdmmc2_d2_pc0 &sdmmc2_d3_pe4
249			&sdmmc2_ck_pc2 &sdmmc2_cmd_pc3>;
250	pinctrl-names = "default";
251	bus-width = <4>;
252	cd-gpios = <&gpion 12 GPIO_ACTIVE_HIGH>;
253	pwr-gpios = <&gpioq 7 GPIO_ACTIVE_HIGH>;
254	disk-name = "SD";
255};
256
257&spi5 {
258	clocks = <&rcc STM32_CLOCK(APB2, 20)>,
259		 <&rcc STM32_SRC_CKPER SPI5_SEL(1)>;
260	pinctrl-0 = <&spi5_nss_pa3 &spi5_sck_pe15 &spi5_miso_ph8 &spi5_mosi_pg2>;
261	pinctrl-names = "default";
262	status = "okay";
263};
264
265&usart1 {
266	clocks = <&rcc STM32_CLOCK(APB2, 4)>,
267		 <&rcc STM32_SRC_CKPER USART1_SEL(1)>;
268	pinctrl-0 = <&usart1_tx_pe5 &usart1_rx_pe6>;
269	pinctrl-names = "default";
270	current-speed = <115200>;
271	status = "okay";
272};
273
274&usart2 {
275	clocks = <&rcc STM32_CLOCK(APB1, 17)>,
276		 <&rcc STM32_SRC_CKPER USART2_SEL(1)>;
277	pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pf6>;
278	pinctrl-names = "default";
279	current-speed = <115200>;
280	status = "okay";
281};
282
283&timers1 {
284	st,prescaler = <9999>;
285	status = "okay";
286
287	pwm1: pwm {
288		status = "okay";
289		pinctrl-0 = <&tim1_ch1_pe9>;
290		pinctrl-names = "default";
291	};
292};
293
294&timers15 {
295	st,prescaler = <9999>;
296	status = "okay";
297
298	pwm15: pwm {
299		status = "okay";
300		pinctrl-0 = <&tim15_ch1_pc12>;
301		pinctrl-names = "default";
302	};
303};
304
305zephyr_udc0: &usbotg_hs1 {
306	status = "okay";
307};
308
309&xspi1 {
310	pinctrl-0 = <&xspim_p1_ncs1_po0 &xspim_p1_dqs0_po2
311		     &xspim_p1_dqs1_po3 &xspim_p1_clk_po4
312		     &xspim_p1_io0_pp0 &xspim_p1_io1_pp1 &xspim_p1_io2_pp2
313		     &xspim_p1_io3_pp3 &xspim_p1_io4_pp4 &xspim_p1_io5_pp5
314		     &xspim_p1_io6_pp6 &xspim_p1_io7_pp7 &xspim_p1_io8_pp8
315		     &xspim_p1_io9_pp9 &xspim_p1_io10_pp10 &xspim_p1_io11_pp11
316		     &xspim_p1_io12_pp12 &xspim_p1_io13_pp13 &xspim_p1_io14_pp14
317		     &xspim_p1_io15_pp15>;
318	pinctrl-names = "default";
319	clocks = <&rcc STM32_CLOCK(AHB5, 5)>,
320		 <&rcc STM32_SRC_HCLK5 XSPI1_SEL(0)>,
321		 <&rcc STM32_CLOCK(AHB5, 13)>;
322	status = "okay";
323
324	memc: aps256xxn_obr: memory@0 {
325		compatible = "st,stm32-xspi-psram";
326		reg = <0>;
327		size = <DT_SIZE_M(256)>; /* 256 Mbits */
328		max-frequency = <DT_FREQ_M(200)>;
329		fixed-latency;
330		io-x16-mode;
331		read-latency = <4>;
332		write-latency = <1>;
333		burst-length = <0>;
334		status = "okay";
335	};
336};
337
338&xspi2 {
339	pinctrl-0 = <&xspim_p2_ncs1_pn1 &xspim_p2_dqs0_pn0 &xspim_p2_clk_pn6
340		     &xspim_p2_io0_pn2 &xspim_p2_io1_pn3 &xspim_p2_io2_pn4
341		     &xspim_p2_io3_pn5 &xspim_p2_io4_pn8 &xspim_p2_io5_pn9
342		     &xspim_p2_io6_pn10 &xspim_p2_io7_pn11>;
343	pinctrl-names = "default";
344	clocks = <&rcc STM32_CLOCK(AHB5, 12)>,
345		 <&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
346		 <&rcc STM32_CLOCK(AHB5, 13)>;
347	status = "okay";
348
349	mx66uw1g45g: ospi-nor-flash@0 {
350		compatible = "st,stm32-xspi-nor";
351		reg = <0>;
352		size = <DT_SIZE_M(1024)>; /* 1Gbits */
353		ospi-max-frequency = <DT_FREQ_M(200)>;
354		spi-bus-width = <XSPI_OCTO_MODE>;
355		data-rate = <XSPI_DTR_TRANSFER>;
356		four-byte-opcodes;
357		status = "okay";
358
359		partitions {
360			compatible = "fixed-partitions";
361			#address-cells = <1>;
362			#size-cells = <1>;
363
364			/*
365			 * Following flash partition is dedicated to the use of bootloader
366			 */
367			boot_partition: partition@0 {
368				label = "mcuboot";
369				reg = <0x00000000 DT_SIZE_K(256)>;
370			};
371
372			slot0_partition: partition@10000 {
373				label = "image-0";
374				reg = <0x10000 DT_SIZE_K(1536)>;
375			};
376
377			slot1_partition: partition@210000 {
378				label = "image-1";
379				reg = <0x210000 DT_SIZE_K(1536)>;
380			};
381
382			storage_partition: partition@410000 {
383				label = "storage";
384				reg = <0x410000 DT_SIZE_K(64)>;
385			};
386		};
387	};
388};
389
390/**
391 * Per the RGMII specification, the Tx clock signal must be skewed
392 * from the Tx data signals by 1~2 ns. On this board, the SoC must
393 * be configured to add the required delay via pinctrl.
394 */
395&eth1_rgmii_gtx_clk_pf0 {
396	st,io-delay-path = "output";
397	st,io-delay-ps = <2000>;
398};
399
400&mac {
401	status = "okay";
402	pinctrl-0 = <&eth1_rgmii_gtx_clk_pf0
403		     &eth1_rgmii_clk125_pf2
404		     &eth1_rgmii_rx_clk_pf7
405		     &eth1_rgmii_rxd2_pf8
406		     &eth1_rgmii_rxd3_pf9
407		     &eth1_rgmii_rx_ctl_pf10
408		     &eth1_rgmii_tx_ctl_pf11
409		     &eth1_rgmii_txd1_pf13
410		     &eth1_rgmii_txd0_pf12
411		     &eth1_rgmii_rxd0_pf14
412		     &eth1_rgmii_rxd1_pf15
413		     &eth1_rgmii_txd2_pg3
414		     &eth1_rgmii_txd3_pg4>;
415	pinctrl-names = "default";
416	phy-connection-type = "rgmii";
417	phy-handle = <&eth_phy>;
418};
419
420&mdio {
421	status = "okay";
422	pinctrl-0 = <&eth1_mdio_pd12 &eth1_mdc_pd1>;
423	pinctrl-names = "default";
424
425	eth_phy: ethernet-phy@1 {
426		compatible = "realtek,rtl8211f";
427		reg = <0x1>;
428		/**
429		 * PD3 can be used as alternate function ETH1_PHY_INTN,
430		 * which allows the Ethernet MAC to sense interrupts from
431		 * the PHY in order to signal them to the CPU via its own
432		 * interrupt lines. However, the Zephyr RTL8211F driver
433		 * is unaware of this mechanism. Skip configuring PD3 as
434		 * alternate function (in pinctrl of &mac) and provide the
435		 * pin to the RTL8211F driver for interrupt sensing using
436		 * the regular GPIO interrupt APIs.
437		 */
438		int-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
439	};
440};
441
442&ltdc {
443	clocks = <&rcc STM32_CLOCK(APB5, 1)>,
444		 <&rcc STM32_SRC_IC16 LTDC_SEL(2)>;
445	pinctrl-0 = <&ltdc_r0_pg0 &ltdc_r1_pd9 &ltdc_r2_pd15 &ltdc_r3_pb4
446			&ltdc_r4_ph4 &ltdc_r5_pa15 &ltdc_r6_pg11 &ltdc_r7_pd8
447			&ltdc_g0_pg12 &ltdc_g1_pg1 &ltdc_g2_pa1 &ltdc_g3_pa0
448			&ltdc_g4_pb15 &ltdc_g5_pb12 &ltdc_g6_pb11 &ltdc_g7_pg8
449			&ltdc_b0_pg15 &ltdc_b1_pa7 &ltdc_b2_pb2 &ltdc_b3_pg6
450			&ltdc_b4_ph3 &ltdc_b5_ph6 &ltdc_b6_pa8 &ltdc_b7_pa2
451			&ltdc_de_pg13 &ltdc_clk_pb13 &ltdc_hsync_pb14 &ltdc_vsync_pe11>;
452	pinctrl-names = "default";
453	disp-on-gpios = <&gpioq 3 GPIO_ACTIVE_HIGH>;
454	bl-ctrl-gpios = <&gpioq 6 GPIO_ACTIVE_HIGH>;
455
456	ext-sdram = <&psram>;
457
458	status = "okay";
459
460	width = <800>;
461	height = <480>;
462	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
463
464	display-timings {
465		compatible = "zephyr,panel-timing";
466		de-active = <0>;
467		pixelclk-active = <0>;
468		hsync-active = <0>;
469		vsync-active = <0>;
470		hsync-len = <4>;
471		vsync-len = <4>;
472		hback-porch = <8>;
473		vback-porch = <8>;
474		hfront-porch = <8>;
475		vfront-porch = <8>;
476	};
477
478	def-back-color-red = <0xFF>;
479	def-back-color-green = <0xFF>;
480	def-back-color-blue = <0xFF>;
481};
482
483csi_interface: &dcmipp {
484	ports {
485		port@0 {
486			csi_ep_in: endpoint { };
487		};
488
489		port@1 {
490			csi_capture_port: endpoint@1 { };
491		};
492	};
493};
494