| /arch/x86/zefi/ |
| A D | zefi.c | 217 unsigned char *code = (void *)zefi_entry; in efi_entry() local
223 code, code[0], code[1], code[2], code[3], in efi_entry()
224 code[4], code[5], code[6]); in efi_entry()
236 :: "r"(&efi_arg), "r"(code) : "rbx"); in efi_entry()
|
| A D | README.txt | 17 Instead, the stub code will copy the embedded zephyr sections to the
32 The code and link environment here is non-obvious. The simple rules
35 1. All code must live in a single C file
41 address is not generated at runtime by the C code here (it's address
46 basically Windows DLLs. But our compiler only generates code for ELF
50 independent code. Non-static global variables and function addresses
|
| /arch/arm/core/cortex_m/ |
| A D | ram_vector_table.ld | 7 /* Vector table is not necessarily at the start of the RAM region: in the case where Zephyr code
8 * relocation is used, the vector table is placed after the relocated code.
9 * Relocated code is always placed at the start of the RAM SECTION because of the hard-coded value
|
| A D | Kconfig | 321 This option instructs the compiler to generate code with all branch protection features
327 This option instructs the compiler to generate code with return address signing for
333 This option instructs the compiler to generate code with return address signing for
347 This option instructs the compiler to generate code with return address signing for
354 This option instructs the compiler to generate code with return address signing for
362 This option instructs the compiler to generate code without branch protection or return
411 code. This option enables the installation of interrupt service
538 increased code footprint, determined by option
554 wasting a large flash area that code may not use.
|
| A D | CMakeLists.txt | 86 # (conflict with code relocation script)
|
| /arch/x86/core/ |
| A D | fatal.c | 223 return esf->code; in esf_get_code()
285 static void log_exception(uintptr_t vector, uintptr_t code) in log_exception() argument
313 EXCEPTION_DUMP("Double fault (code 0x%lx)", code); in log_exception()
319 EXCEPTION_DUMP("Invalid TSS (code 0x%lx)", code); in log_exception()
322 EXCEPTION_DUMP("Segment not present (code 0x%lx)", code); in log_exception()
328 EXCEPTION_DUMP("General protection fault (code 0x%lx)", code); in log_exception()
335 EXCEPTION_DUMP("Alignment check (code 0x%lx)", code); in log_exception()
350 EXCEPTION_DUMP("Exception not handled (code 0x%lx)", code); in log_exception()
|
| A D | Kconfig.ia32 | 161 some stub code to be generated at build time, one stub per dynamic
|
| /arch/x86/core/intel64/ |
| A D | coredump.c | 15 uint64_t code; member
66 arch_blk.code = esf->code; in arch_coredump_info_dump()
|
| /arch/arm/core/ |
| A D | Kconfig | 81 efficiency, and code density for a wide range of embedded
92 benefit from the best in class code density of Thumb.
94 For performance optimized code Thumb-2 technology uses 31 percent
128 because the architecture assembly code makes use of the ARM
141 "compiled" code.
174 executed at the beginning of the startup code (__start).
227 This option enables Zephyr to include code that executes in
228 Secure state, as well as to exclude code that is designed to
236 Secure Faults may only be handled by code executing in Secure
251 This option enables Zephyr to include code that executes in
[all …]
|
| A D | Kconfig.vfp | 154 # support code to resolve the supported VFP features.
|
| /arch/x86/core/ia32/ |
| A D | coredump.c | 15 uint32_t code; member
54 arch_blk.code = esf->errorCode; in arch_coredump_info_dump()
|
| /arch/posix/ |
| A D | Kconfig.natsim_optional | 7 Build the native simulator nsi_errno component with the Zephyr embedded code.
|
| /arch/xtensa/core/ |
| A D | fatal.c | 120 : [code] "r" (return_code), [call] "i" (SYS_exit) in xtensa_simulator_exit()
|
| A D | README_MMU.txt | 31 userspace code.
40 initialization, but this mechanism isn't accessible to OS code except
66 occupied by the running code. The 1024 pages in that range (not all
145 execute code before the OS is able to initialize a refillable page
184 an ASID of zero. This is safe as the code being executed is not
190 code page will then cause a TLB refill exception, which will work
194 exception handlers first so the trap from our current code can be
|
| A D | xtensa_intgen.tmpl | 4 * Not a C source code file.
|
| /arch/arc/ |
| A D | Kconfig | 138 Disabling this option removes usage of ZOL regs from code
283 Enable code density option to get better code density
307 code in normal mode call secure services in secure mode through
319 This option enables Zephyr to include code that executes in
320 secure mode, as well as to exclude code that is designed to
338 This option enables Zephyr to include code that executes in
339 normal mode only, as well as to exclude code that is
410 Call SoC per-core setup code on early stage initialization
411 (before C runtime initialization). Setup code is called in form of
|
| A D | CMakeLists.txt | 35 # instead of full 64bit address in ASM code. It is valid as we don't support Zephyr
|
| /arch/riscv/ |
| A D | Kconfig | 29 the code size.
64 bool "Medium-low code model"
70 bool "Medium-any code model"
73 within any single 2 GiB address range. The code generated by this model is
77 bool "Large code model"
79 In large code model (large), the program and its statically defined symbols have no
141 IRQ wrapper assembly code on ISR entry to save in the ESF the
146 IRQ wrapper assembly code on ISR exit to restore the part of the
210 architecture code will allocate space for these members in
283 Specify the bits to use for exception code in mcause register.
[all …]
|
| A D | Kconfig.isa | 99 which reduces static and dynamic code size by adding short 16-bit
157 The Zcb extension is a set of simple code-size saving instructions
|
| /arch/common/ |
| A D | Kconfig | 10 Semihosting is a mechanism that enables code running on an ARM, RISC-V
70 policy allows instruction fetches by privileged code, forcing
73 execute code from SRAM in XIP builds.
|
| /arch/xtensa/ |
| A D | Kconfig | 18 bool "Build reset vector code"
21 This option controls whether the initial reset vector code is built.
30 containing definitions for the interrupt entry code of the
285 # TODO: the target the MPU code developed on (basically sample_controller
307 Enable this by the SoC to indicate to the architecture code to use
309 defined in the core architecture code. This gives total control to
|
| /arch/arm/core/cortex_m/tz/ |
| A D | CMakeLists.txt | 3 # '-mcmse' enables the generation of code for the Secure state of the ARMv8-M
|
| /arch/arm/ |
| A D | Kconfig | 63 for code location. But the boot-vector must be placed into OCRAM_S for the
103 bool "Relocate code/data sections to SRAM"
110 config is used to create an MPU entry for the SRAM space used for code
134 Enables a possibility to inject SoC-specific code just after WFI/WFE
|
| /arch/arm64/core/ |
| A D | CMakeLists.txt | 20 # Use large code model for addresses larger than 32 bits,
|
| /arch/ |
| A D | Kconfig | 37 # FIXME: current state of the code for all ARM requires this, but
489 on some architectures increase code size.
525 supplied by the application or architecture code.
555 bool "Jump by code"
634 make debugging them easier, at a small expense in code size.
962 code on an ARCH-specific basis. Refer to ARCH-specific
1001 bool "Support code/data section relocation"
1055 if it is guaranteed that the image code does not generate FP
1093 driver code.
1101 code and a slightly increased boot time.
[all …]
|