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/arch/arm/core/
A Dfatal.c39 for (int i = 0; i < ARRAY_SIZE(esf->fpu.d); i += 4) { in esf_dump()
42 i, (uint64_t)esf->fpu.d[i], in esf_dump()
43 i + 1, (uint64_t)esf->fpu.d[i + 1], in esf_dump()
44 i + 2, (uint64_t)esf->fpu.d[i + 2], in esf_dump()
45 i + 3, (uint64_t)esf->fpu.d[i + 3]); in esf_dump()
/arch/x86/zefi/
A Dprintf.h123 int d = (v >> (i*4)) & 0xf; in vpf() local
125 sig += !!d; in vpf()
127 pc(r, "0123456789abcdef"[d]); in vpf()
A DREADME.txt75 a IP-relative addressing mode, so we'd have to do some kind of
/arch/arc/core/secureshield/
A Darc_secure.S87 j.d [blink]
106 j.d [blink]
/arch/arc/core/
A Dcpu_idle.S75 j_s.d [blink]
A Dregular_irq.S216 bne.d rirq_nest
A Duserspace.S278 j_s.d [blink]
283 brne.d.nt lp_count, 0x1, inc_len
A Disr_wrapper.S306 jl_s.d [r1]
A Dfast_irq.S80 bne.d firq_nest
/arch/arc/include/
A Dswap_macros.h555 .macro _st32_huge_offset, d, s, offset, temp
557 st MACRO_ARG(d), [MACRO_ARG(s), MACRO_ARG(offset)]
565 st.as MACRO_ARG(d), [MACRO_ARG(s), MACRO_ARG(offset) >> __arc_ldst32_as_shift]
568 st MACRO_ARG(d), [MACRO_ARG(temp)]
/arch/common/
A DCMakeLists.txt100 # should not be --whole-archive'd
/arch/arm/core/cortex_a_r/
A Dfault.c187 : "r" (&fpu->d[0]) in z_arm_fpu_caller_save()
/arch/
A DKconfig873 This hidden configuration should be selected when the CPU has a d-cache.
1064 bool "Data cache (d-cache) support"
1068 This option enables the support for the data cache (d-cache).
1096 bool "Detect d-cache line size at runtime"
1100 finding the d-cache line size at the expense of taking more memory and
1103 If the CPU's d-cache line size is known in advance, disable this option and
1105 using the 'd-cache-line-size' property.
1108 int "d-cache line size"
1112 Size in bytes of a CPU d-cache line. If this is set to 0 the value is
1113 obtained from the 'd-cache-line-size' DT property instead if present.

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