Searched refs:f (Results 1 – 25 of 27) sorted by relevance
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| /arch/xtensa/core/ |
| A D | gen_zsr.py | 66 regs.append(f"EXCSAVE{il}")
87 with open(outfile, "w") as f:
92 f.write(f"# define ZSR_{need} {regs[i]}\n")
93 f.write(f"# define ZSR_{need}_STR \"{regs[i]}\"\n")
97 f.write(f"# define ZSR_EXTRA{i - len(NEEDED)} {regs[i]}\n")
98 f.write(f"# define ZSR_EXTRA{i - len(NEEDED)}_STR \"{regs[i]}\"\n")
101 f.write(f"# define ZSR_RFI_LEVEL {maxint}\n")
102 f.write(f"# define ZSR_EPC EPC{maxint}\n")
103 f.write(f"# define ZSR_EPS EPS{maxint}\n")
107 f.write(f"# define ZSR_IRQ_OFFLOAD_INT {irqoff_int}\n")
[all …]
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| A D | gen_vectors.py | 84 print(f"no intlevel match for debug val {val}")
96 offsets[f"Level{m.group(1)}Interrupt"] = addr
101 old = f"Level{debug_level}Interrupt"
102 offsets[f"DebugException"] = offsets[old]
117 print(f" KEEP(*(.WindowVectors.text));")
119 print(f" KEEP(*(.{s}Vector.literal));")
121 print(f" KEEP(*(.{s}Vector.text));")
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| A D | crt1.S | 139 beqz a4, 1f
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| /arch/x86/zefi/ |
| A D | printf.h | 72 for (/**/; *f != '\0'; f++) { in vpf()
75 if (*f != '%') { in vpf()
76 pc(r, *f); in vpf()
82 f++; in vpf()
86 while (f[1] >= '0' && f[1] <= '9') { in vpf()
87 f++; in vpf()
90 f++; in vpf()
92 while (f[1] >= '0' && f[1] <= '9') { in vpf()
93 f++; in vpf()
96 switch (*(++f)) { in vpf()
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| A D | zefi.py | 68 verbose(f"{len(data_blob)} bytes of data to include in image")
165 verbose(f"Working on {args.elf_file} with {args.includes}...")
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| /arch/arm64/core/ |
| A D | early_mem_funcs.S | 27 b.ne 2f
31 b.lo 2f
45 cbz x2, 4f
61 b.ne 2f
65 b.lo 2f
75 cbz x2, 4f
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| A D | reset.S | 45 switch_el x0, 3f, 2f, 1f
149 beq 1f
221 switch_el x0, 3f, 2f, 1f
242 adr x0, 1f
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| A D | userspace.S | 65 cbnz w2, 1f
67 b 2f
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| A D | switch.S | 156 bne 1f
196 cbnz w3, 1f
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| A D | macro_priv.inc | 37 beq 2f
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| A D | vector_table.S | 266 ble 1f
325 bne 1f
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| A D | isr_wrapper.S | 42 cbnz w1, 1f
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| /arch/x86/core/ |
| A D | common.S | 27 je 1f
69 jmp 1f
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| /arch/riscv/core/ |
| A D | isr.S | 152 bnez t0, 1f
234 bnez t2, 1f
267 bnez t1, 2f /* not a CSR insn */
272 beqz t0, 2f /* 0=ustatus */
377 bnez t0, 1f
456 j 1f
501 bnez t1, 1f
600 bnez t0, 1f
603 j 2f
773 bnez t0, 1f
[all …]
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| A D | asm_macros.inc | 62 beqz \rs, 999f
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| /arch/x86/core/ia32/ |
| A D | excstub.S | 110 jz 1f
115 jmp 2f
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| A D | userspace.S | 47 jz 1f
107 jz 1f
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| A D | intstub.S | 444 jmp 1f
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| /arch/arc/core/ |
| A D | reset.S | 94 and.f r0, r0, 0xff
107 and.f r3, r3, 0xff
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| /arch/xtensa/core/startup/ |
| A D | reset_vector.S | 215 bltui a2, 12, 1f
255 bbci.l a7, PWRSTAT_WAKEUP_RESET_SHIFT, 1f
262 bnez a4, 1f
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| /arch/arm/core/cortex_a_r/ |
| A D | macro_priv.inc | 34 beq 2f
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| A D | switch.S | 140 bhi 1f
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| A D | reset.S | 233 beq 1f
276 b 2f
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| /arch/x86/core/intel64/ |
| A D | locore.S | 138 jmpl $X86_KERNEL_CS_32, $1f
331 jz 1f
468 jz 1f
484 jz 1f
540 jz 1f
631 jz 1f
695 jz 1f
737 jz 1f
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| /arch/rx/core/ |
| A D | reset.S | 40 beq 2f
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Completed in 33 milliseconds
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