Searched refs:handler (Results 1 – 15 of 15) sorted by relevance
| /arch/x86/include/ia32/ |
| A D | exception.h | 27 #define __EXCEPTION_STUB_NAME(handler, vec) \ argument
28 _ ## handler ## _vector_ ## vec ## _stub
30 #define _EXCEPTION_STUB_NAME(handler, vec) \ argument
31 __EXCEPTION_STUB_NAME(handler, vec) \
44 #define __EXCEPTION_CONNECT(handler, vector, dpl, codepush) \ argument
50 STRINGIFY(_EXCEPTION_STUB_NAME(handler, vector)) ":\n\t" \
53 "push $" STRINGIFY(handler) "\n\t" \
68 #define _EXCEPTION_CONNECT_NOCODE(handler, vector, dpl) \ argument
69 __EXCEPTION_CONNECT(handler, vector, dpl, "push $0\n\t")
81 #define _EXCEPTION_CONNECT_CODE(handler, vector, dpl) \ argument
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| /arch/arm/core/ |
| A D | nmi.c | 25 #define handler z_SysNmiOnReset macro
30 static _NmiHandler_t handler = z_SysNmiOnReset; variable
44 handler = pHandler; in z_arm_nmi_set_handler()
58 handler(); in z_arm_nmi()
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| A D | Kconfig | 161 bool "Attach an NMI handler at runtime"
164 The kernel provides a simple NMI handler that simply hangs in a tight
166 NMI handler installed when the CPU boots. If a custom handler is
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| /arch/x86/ |
| A D | gen_idt.py | 64 def create_irq_gate(handler, dpl): argument
69 offset_hi = handler >> 16
70 offset_lo = handler & 0xFFFF
89 if handler and tss:
92 if not handler and not tss:
95 if handler:
154 vectors[vec] = (handler, tss, dpl)
172 vectors[vec] = (handler, tss, dpl)
181 handler = spur_code
183 handler = spur_nocode
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| A D | Kconfig | 482 Zephyr printk handler. It requires that no interferences
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| /arch/x86/core/ia32/ |
| A D | irq_manage.c | 26 extern void z_SpuriousIntHandler(void *handler);
27 extern void z_SpuriousIntNoErrCodeHandler(void *handler);
59 void (*handler)(const void *param); member
222 dyn_irq_list[stub_idx].handler = routine; in arch_irq_connect_dynamic()
243 dyn_irq_list[stub_idx].handler(dyn_irq_list[stub_idx].param); in z_x86_dynamic_irq_handler()
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| /arch/sparc/core/ |
| A D | trap_table_mvt.S | 28 #define TRAP(handler) \ argument
30 sethi %hi(handler), %l4; \
31 jmp %l4+%lo(handler); \
34 #define RESET_TRAP(handler) \ argument
36 sethi %hi(handler), %g4; \
37 jmp %g4+%lo(handler); \
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| /arch/arm/core/cortex_a_r/ |
| A D | Kconfig | 50 This option specifies the size of the stack used by the FIQ handler.
56 This option specifies the size of the stack used by the SVC handler.
201 This option specifies the size of the stack used by the FIQ handler.
207 This option specifies the size of the stack used by the SVC handler.
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| /arch/xtensa/core/ |
| A D | README_MMU.txt | 83 The job of that exception handler is simply to ensure that the TLB has
87 the exception handler may result in an invalid/inapplicable mapping
90 exception from within the TLB miss exception handler (i.e. while the
123 done in an exception handler. And running an exception handler
125 means that the page(s) containing the exception handler must never
128 Ideally we would just pin the vector/handler page in the ITLB in the
176 exception handler into the data TLB. This will likewise not be
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| A D | README_WINDOWS.rst | 63 spilled and the CPU traps to an exception handler to fill them.
68 handler to spill one frame. Note that a frame might be only four
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| /arch/riscv/ |
| A D | Kconfig | 47 bool "Do not use mret outside a trap handler context"
50 Use mret instruction only when in a trap handler.
485 int "Alignment of RISC-V trap handler in bytes"
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| /arch/ |
| A D | Kconfig | 552 The IRQ vector table contains the address of the interrupt handler.
558 interrupt handler address.
659 bool "Create empty spurious interrupt handler"
662 This option changes body of spurious interrupt handler. When enabled,
663 handler contains only an infinite while loop, when disabled, handler
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| /arch/x86/core/ |
| A D | Kconfig.ia32 | 59 do privilege elevation. It also defines a special TSS and handler
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| /arch/arc/ |
| A D | Kconfig | 171 register bank, the fast interrupt handler must save
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| /arch/arm/core/cortex_m/ |
| A D | Kconfig | 420 vector table relay handler and a vector relay table, to
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