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Searched refs:level (Results 1 – 21 of 21) sorted by relevance

/arch/common/
A Dmultilevel_irq.c30 const unsigned int level = irq_get_level(irq); in get_intc_entry_for_irq() local
33 if (level == 1) { in get_intc_entry_for_irq()
41 if ((intc->level == level) && (intc->irq == intc_irq)) { in get_intc_entry_for_irq()
76 const unsigned int level = irq_get_level(irq); in z_get_sw_isr_table_idx() local
79 local_irq = irq_from_level(irq, level); in z_get_sw_isr_table_idx()
85 __ASSERT(level == 1, "can't find an aggregator to handle irq(%X)", irq); in z_get_sw_isr_table_idx()
/arch/x86/core/
A Dx86_mmu.c348 return get_entry_scope(level) * get_num_entries(level); in get_table_scope()
372 for (int level = 0; level < NUM_LEVELS; level++) { in pentry_get() local
665 if (level == 0) { in dump_ptables()
692 level + 1); in dump_ptables()
779 int level = 0; in z_x86_dump_mmu_flags() local
825 int level) in pte_finalize_value() argument
1011 for (int level = 0; level < NUM_LEVELS; level++) { in page_map_set() local
1399 for (int level = 0; level < NUM_LEVELS; level++) { in page_validate() local
2070 int level, ret; in arch_page_phys_get() local
2208 int level; in arch_page_location_get() local
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A DKconfig.intel6470 level. Must be a multiple of 16 to main stack alignment. Note that
90 supporting user-level threads that are protected from each other and
A DKconfig.ia3285 supporting user-level threads that are protected from each other and
/arch/arm64/core/
A Dmmu.c186 unsigned int level) in is_desc_superset() argument
241 debug_show_pte(pte, level); in set_pte_table_desc()
257 debug_show_pte(pte, level); in set_pte_block_desc()
323 level++; in set_mapping()
332 level, pte, *pte); in set_mapping()
354 level++; in set_mapping()
372 level = BASE_XLAT_LEVEL; in set_mapping()
379 unsigned int level) in del_mapping() argument
1169 int level; in arch_virt_region_align() local
1171 for (level = XLAT_LAST_LEVEL; level >= BASE_XLAT_LEVEL; level--) { in arch_virt_region_align()
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A Dmmu.h49 #define LEVEL_TO_VA_SIZE_SHIFT(level) \ argument
51 (XLAT_LAST_LEVEL - (level))))
57 #define XLAT_TABLE_VA_IDX(va_addr, level) \ argument
58 ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (Ln_XLAT_NUM_ENTRIES - 1))
A DKconfig236 virtualization at the highest security level while retaining the
284 space sizes. The level of translation table is determined by
/arch/x86/
A Dgen_mmu.py367 def is_mapped(self, virt_addr, level): argument
376 num_levels = len(self.levels) + level + 1
398 if self.is_mapped(vaddr, level):
419 num_levels = len(self.levels) + level + 1
470 scope = 1 << self.levels[level].addr_shift
488 scope = 1 << self.levels[level].addr_shift
539 num_levels = len(self.levels) + level + 1
540 scope = 1 << self.levels[level].addr_shift
714 if pt.is_region_mapped(virt, size, level):
719 pt.reserve_unaligned(virt, size, level)
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/arch/xtensa/core/startup/
A Dreset_vector.S637 .macro init_vector level
638 .if GREATERTHAN(XCHAL_NUM_INTLEVELS+1,\level)
639 .if XCHAL_DEBUGLEVEL-\level
640 .weak _Level&level&FromVector
641 movi a4, _Level&level&FromVector
642 wsr a4, EXCSAVE+\level
643 .if GREATERTHAN(\level,XCHAL_EXCM_LEVEL)
644 movi a5, _Pri_&level&_HandlerAddress
653 .global _Pri_&level&_HandlerAddress
654 .weak _Pri_&level&_HandlerAddress
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/arch/arm/core/mmu/
A DKconfig25 Number of level 2 translation tables. Each level 2 table
/arch/arm64/
A DKconfig30 implemented at the SoC level.
/arch/sparc/core/
A Dtrap_table_mvt.S22 #define INTERRUPT_TRAP(level) \ argument
26 mov (0xf & level), %l3;
/arch/xtensa/core/
A Dxtensa_intgen.tmpl8 * this does is emit records for which interrupts are at which level,
A DREADME_MMU.txt6 to introduce the architecture at an overview/tutorial level, and to
119 one of these to "pin" the top-level page table entry in place,
156 But that means that enabling page-level translation requires some
162 top-level "L1" page containing the mappings for the page table
205 page-level control over physical memory (e.g. .text/.rodata is cached
/arch/arc/
A DKconfig173 NOTE: it's required to have more than one interrupt priority level
191 interrupt priority level (so all interrupts are FIRQ). Such
382 bool "System level cache"
393 Size in bytes of a CPU system level cache line.
/arch/riscv/
A DKconfig128 Enable low-level SOC-specific hardware stacking / unstacking
199 Enable low-level SOC-specific context management, for SOCs
260 For CLIC implementations with extended interrupt level, where
262 levels. This option handles interrupt level in ISR to ensure proper
/arch/arm/core/cortex_m/
A DKconfig140 the same or lower priority level as the BASEPRI value.
178 therefore, it needs to reserve a priority level for them.
322 enabled at their standard level.
403 level for zero latency interrupts.
/arch/arm/core/cortex_a_r/
A DKconfig186 virtualization at the highest security level while retaining the
/arch/arm/
A DKconfig31 implemented at the SoC level.
/arch/
A DKconfig18 # Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
176 symbols above. See the top-level CMakeLists.txt.
651 a multitude of potential exception codes at the CPU level, depending
673 of the internal architectural state (for example ARCH-level
/arch/arm/core/
A DKconfig179 int "Fault dump level"

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