Searched refs:loop (Results 1 – 4 of 4) sorted by relevance
31 loop: label46 j loop
133 ARCv2 CPUs have ZOL hardware loop mechanism which the ARCv3 ISA drops.378 Perform L1 data cache management operations by regions rather than line by line in a loop,
165 loop if triggered. This fills the requirement that there must be an
663 handler contains only an infinite while loop, when disabled, handler
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