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Searched refs:m (Results 1 – 8 of 8) sorted by relevance

/arch/xtensa/core/
A Dgen_vectors.py67 m = re.match(r"^#define\s+XCHAL_([^ ]+)_VECOFS\s*(.*)", line.rstrip()) variable
68 if m:
69 (sym, val) = (m.group(1), m.group(2))
82 m = re.match(r"XCHAL_INTLEVEL(\d+)_VECOFS", val) variable
83 if not m:
85 assert m
86 debug_level = eval(m.group(1))
94 m = re.match(r"^INTLEVEL(\d+)", sym) variable
95 if m:
A Dvector_handlers.c392 irqs ^= m; \
393 __asm__ volatile("wsr.intclear %0" : : "r"(m)); \
409 irqs ^= m; \
410 __asm__ volatile("wsr.intclear %0" : : "r"(m)); \
416 irqs ^= m; \
417 __asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \
433 irqs ^= m; \
434 __asm__ volatile("wsr.intclear %0" : : "r"(m)); \
440 irqs ^= m; \
441 __asm__ volatile("wsr.intclear1 %0" : : "r"(m)); \
[all …]
A Dgen_zsr.py48 m = re.match(r"^#define\s+([^ ]+)\s*(.*)", line.rstrip()) variable
49 if m:
50 syms[m.group(1)] = m.group(2)
76 m = re.match(r"XCHAL_INT(\d+)_TYPE", sym) variable
77 if m:
78 intnum = int(m.group(1))
A Dxtensa_intgen.py52 m = 0
54 m |= 1 << i
55 cprint("if (mask & " + ("0x%x" % (m)) + ") {")
/arch/x86/core/
A Dpcie.c39 struct acpi_mcfg *m = acpi_table_get("MCFG", 0); in pcie_mm_init() local
41 if (m != NULL) { in pcie_mm_init()
42 int n = (m->header.Length - sizeof(*m)) / sizeof(m->pci_segs[0]); in pcie_mm_init()
48 bus_segs[i].start_bus = m->pci_segs[i].StartBusNumber; in pcie_mm_init()
50 1 + m->pci_segs[i].EndBusNumber - m->pci_segs[i].StartBusNumber; in pcie_mm_init()
52 phys_addr = m->pci_segs[i].Address; in pcie_mm_init()
/arch/arm/core/mpu/
A DKconfig77 Enable support for Armv8.1-m MPU's Privileged Execute Never (PXN) attr.
/arch/common/
A DKconfig14 https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
/arch/arm/core/cortex_m/
A DKconfig240 From https://developer.arm.com/products/architecture/m-profile:

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