Searched refs:paddr (Results 1 – 3 of 3) sorted by relevance
| /arch/xtensa/include/ |
| A D | xtensa_mmu_priv.h | 68 #define XTENSA_MMU_PTE(paddr, ring, sw, attr) \ argument
69 (((paddr) & XTENSA_MMU_PTE_PPN_MASK) | \
438 uint32_t paddr; in xtensa_dtlb_paddr_read() local
440 __asm__ volatile("rdtlb1 %0, %1\n\t" : "=a" (paddr) : "a" (entry)); in xtensa_dtlb_paddr_read()
441 return (paddr & XTENSA_MMU_PTE_PPN_MASK); in xtensa_dtlb_paddr_read()
464 uint32_t paddr; in xtensa_itlb_paddr_read() local
466 __asm__ volatile("ritlb1 %0, %1\n\t" : "=a" (paddr), "+a" (entry)); in xtensa_itlb_paddr_read()
467 return (paddr & XTENSA_MMU_PTE_PPN_MASK); in xtensa_itlb_paddr_read()
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| /arch/xtensa/core/ |
| A D | ptables.c | 401 uintptr_t paddr, paddr_uc; in __arch_mem_map() local
414 paddr = pa; in __arch_mem_map()
417 paddr = (uintptr_t)sys_cache_cached_ptr_get((void *)pa); in __arch_mem_map()
425 paddr = pa; in __arch_mem_map()
429 ret = l2_page_table_map(xtensa_kernel_ptables, (void *)vaddr, paddr, in __arch_mem_map()
451 ret = l2_page_table_map(domain->ptables, (void *)vaddr, paddr, in __arch_mem_map()
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| /arch/x86/ |
| A D | gen_mmu.py | 477 for paddr in range(phys_base, phys_base + size, scope):
478 if is_identity_map and paddr == 0 and level == PT_LEVEL:
482 vaddr = virt_base + (paddr - phys_base)
484 self.map_page(vaddr, paddr, flags, False, level)
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