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/arch/xtensa/core/
A DREADME_MMU.txt23 and data spaces, but the hardware page table refill mechanism (see
84 an entry for the page table page we want. And the simplest way to do
114 page of PTE entries (which itself lives in the 4M page table region!).
115 This page must always be in the TLB.
119 one of these to "pin" the top-level page table entry in place,
136 the page table page containing the (single) PTE for the vector page in
162 top-level "L1" page containing the mappings for the page table
175 3. Pin the page table page containing the PTE for the TLB miss
192 (Pedantic note: if the vector page and the currently-executing page
224 smaller than the 1024-page PTE array).
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A Dptables.c208 uint32_t page, *table; in map_memory_range() local
213 for (page = start; page < end; page += CONFIG_MMU_PAGE_SIZE) { in map_memory_range()
214 uint32_t pte = XTENSA_MMU_PTE(page, in map_memory_range()
218 uint32_t l2_pos = XTENSA_MMU_L2_POS(page); in map_memory_range()
219 uint32_t l1_pos = XTENSA_MMU_L1_POS(page); in map_memory_range()
225 "map 0x%08x\n", page); in map_memory_range()
351 uintptr_t page; in arch_reserved_pages_update() local
355 page < (uintptr_t)z_mapped_start; in arch_reserved_pages_update()
356 page += CONFIG_MMU_PAGE_SIZE, idx++) { in arch_reserved_pages_update()
857 uint32_t page = start + offset; in region_map_update() local
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/arch/x86/zefi/
A Defi.ld20 * need to be page-aligned and can be immediately after text/rodata */
23 /* Must be page-aligned or EFI balks */
/arch/x86/
A DKconfig208 This value normally need to be page-aligned.
328 and creates a set of page tables at boot time that is runtime-
332 bool "Use a single page table for all threads"
341 for page tables.
351 memory pages for constructing page tables.
356 int "Reserve extra pages in page table"
361 The whole page table is pre-allocated at build time and is
363 extra pages (of size CONFIG_MMU_PAGE_SIZE) to the page table
457 bool "Kernel page table isolation"
465 increase for additional page tables and trampoline stacks.
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A DCMakeLists.txt34 # Always set for 64-bit (long mode requires page tables), optional for 32-bit
/arch/xtensa/
A DKconfig218 The virtual address for Xtensa page table (PTEVADDR).
229 The virtual address for Xtensa page table (PTEVADDR).
236 page table (PTEVADDR).
239 int "Number of L1 page tables"
248 int "Number of L2 page tables"
265 bool "Flush all auto-refill data TLBs when swapping page tables"
268 This flushes (invalidates) all auto-refill data TLBs when page
/arch/arm/core/mmu/
A DKconfig32 Minimum size (and alignment) of an ARM MMU page.
/arch/x86/core/
A DKconfig.ia3274 by preceding all stack areas with a 4K guard page.
89 bool "Use PAE page tables"
93 If enabled, use PAE-style page tables instead of 32-bit page tables.
A DKconfig.intel6482 by preceding all stack areas with a 4K guard page.
A Dx86_mmu.c393 char *page = (char *)addr; in tlb_flush_page() local
395 __asm__ ("invlpg %0" :: "m" (*page)); in tlb_flush_page()
/arch/
A DKconfig746 Architecture code supports page tracking for eviction algorithms
859 certain RAM page frames need to be marked as reserved and never used for
892 If RAM starts at 0x0, the first page must remain un-mapped to catch NULL
903 virtual address space. The kernel's page frame ontology will not consider
/arch/arm64/core/
A DKconfig285 a combination of page size and virtual address space size.
/arch/arm/core/cortex_m/
A DKconfig551 Size of the page reserved for detecting null pointer

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