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Searched refs:reg (Results 1 – 16 of 16) sorted by relevance

/arch/arm64/core/
A Dreset.c71 uint64_t reg; in z_arm64_el3_init() local
81 write_cptr_el3(reg); in z_arm64_el3_init()
83 reg = 0U; /* Reset */ in z_arm64_el3_init()
96 write_scr_el3(reg); in z_arm64_el3_init()
123 uint64_t reg; in z_arm64_el2_init() local
144 write_sctlr_el2(reg); in z_arm64_el2_init()
146 reg = read_hcr_el2(); in z_arm64_el2_init()
154 write_hcr_el2(reg); in z_arm64_el2_init()
160 write_cptr_el2(reg); in z_arm64_el2_init()
187 uint64_t reg; in z_arm64_el1_init() local
[all …]
/arch/riscv/core/
A Dswitch.S17 #define DO_CALLEE_SAVED(op, reg) \ argument
18 RV_E( op ra, _thread_offset_to_ra(reg) );\
19 RV_E( op s0, _thread_offset_to_s0(reg) );\
20 RV_E( op s1, _thread_offset_to_s1(reg) );\
21 RV_I( op s2, _thread_offset_to_s2(reg) );\
22 RV_I( op s3, _thread_offset_to_s3(reg) );\
23 RV_I( op s4, _thread_offset_to_s4(reg) );\
24 RV_I( op s5, _thread_offset_to_s5(reg) );\
25 RV_I( op s6, _thread_offset_to_s6(reg) );\
26 RV_I( op s7, _thread_offset_to_s7(reg) );\
[all …]
/arch/xtensa/core/
A Dgdbstub.c121 regno = reg->regno & 0xFF; in read_sreg()
333 reg->val = val; in read_sreg()
470 reg->val = bsa[reg->stack_offset / 4]; in copy_to_ctx()
484 reg->val = bsa[reg->stack_offset / 4]; in copy_to_ctx()
487 read_sreg(ctx, reg); in copy_to_ctx()
555 ((uint32_t *)bsa)[reg->stack_offset / 4] = reg->val; in restore_from_ctx()
567 ((uint32_t *)bsa)[reg->stack_offset / 4] = reg->val; in restore_from_ctx()
697 reg = &ctx->regs[idx]; in arch_gdb_reg_readall()
836 (uint8_t *)&reg->val, reg->byte_size); in arch_gdb_reg_writeone()
971 uint32_t reg; in z_gdb_isr() local
[all …]
A DCMakeLists.txt104 $<$<BOOL:${NEED_FLUSH_SCRATCH_REG}>:--flush-reg>
/arch/x86/core/
A Dearly_serial.c20 #define IN(reg) sys_in8(reg + DT_REG_ADDR(DT_CHOSEN(zephyr_console))) argument
21 #define OUT(reg, val) sys_out8(val, reg + DT_REG_ADDR(DT_CHOSEN(zephyr_console))) argument
28 #define IN(reg) (sys_read32(mmio + (reg) * 4) & 0xff) argument
29 #define OUT(reg, val) sys_write32((val) & 0xff, mmio + (reg) * 4) argument
40 #define IN(reg) sys_read8(BASE + reg) argument
41 #define OUT(reg, val) sys_write8(val, BASE + reg) argument
A Dpcie.c65 static inline void pcie_mm_conf(pcie_bdf_t bdf, unsigned int reg, in pcie_mm_conf() argument
80 regs[reg] = *data; in pcie_mm_conf()
82 *data = regs[reg]; in pcie_mm_conf()
104 static inline void pcie_io_conf(pcie_bdf_t bdf, unsigned int reg, in pcie_io_conf() argument
112 bdf |= (reg & PCIE_X86_CAP_WORD_MASK) << PCIE_X86_CAP_WORD_SHIFT; in pcie_io_conf()
127 static inline void pcie_conf(pcie_bdf_t bdf, unsigned int reg, in pcie_conf() argument
137 pcie_mm_conf(bdf, reg, write, data); in pcie_conf()
141 pcie_io_conf(bdf, reg, write, data); in pcie_conf()
147 uint32_t pcie_conf_read(pcie_bdf_t bdf, unsigned int reg) in pcie_conf_read() argument
151 pcie_conf(bdf, reg, false, &data); in pcie_conf_read()
[all …]
/arch/mips/include/mips/
A Dmipsregs.h33 #define _mips_read_32bit_c0_register(reg) \ argument
36 __asm__ __volatile__("mfc0\t%0, " STRINGIFY(reg) "\n" \
41 #define _mips_write_32bit_c0_register(reg, val) \ argument
43 __asm__ __volatile__("mtc0 %z0, " STRINGIFY(reg) "\n" \
/arch/mips/core/
A Disr.S22 #define DO_CALLEE_SAVED(op, reg) \ argument
23 op s0, THREAD_O(s0)(reg) ;\
24 op s1, THREAD_O(s1)(reg) ;\
25 op s2, THREAD_O(s2)(reg) ;\
26 op s3, THREAD_O(s3)(reg) ;\
27 op s4, THREAD_O(s4)(reg) ;\
28 op s5, THREAD_O(s5)(reg) ;\
29 op s6, THREAD_O(s6)(reg) ;\
30 op s7, THREAD_O(s7)(reg) ;\
31 op s8, THREAD_O(s8)(reg) ;
[all …]
/arch/arc/include/
A Dswap_macros.h382 xbfu MACRO_ARG(reg), MACRO_ARG(reg), 0xe8
405 PUSHR MACRO_ARG(reg)
410 POPR MACRO_ARG(reg)
518 bclr MACRO_ARG(reg), MACRO_ARG(reg), _ARC_V2_SEC_STAT_SSC_BIT
519 sflag MACRO_ARG(reg)
523 bclr MACRO_ARG(reg), MACRO_ARG(reg), _ARC_V2_STATUS32_SC_BIT
524 kflag MACRO_ARG(reg)
536 bset MACRO_ARG(reg), MACRO_ARG(reg), _ARC_V2_SEC_STAT_SSC_BIT
537 sflag MACRO_ARG(reg)
540 bset MACRO_ARG(reg), MACRO_ARG(reg), _ARC_V2_STATUS32_SC_BIT
[all …]
/arch/arm/core/mpu/
A Dnxp_mpu.c148 #define _BUILD_REGION_CONF(reg, _ATTR) \ argument
149 (struct nxp_mpu_region) { .name = (reg).dt_name, \
150 .base = (reg).dt_addr, \
151 .end = (reg).dt_addr + (reg).dt_size, \
A Darm_mpu.c100 #define _BUILD_REGION_CONF(reg, _ATTR) \ argument
101 (struct arm_mpu_region) ARM_MPU_REGION_INIT((reg).dt_name, \
102 (reg).dt_addr, \
103 (reg).dt_size, \
/arch/arm64/core/cortex_r/
A Darm_mpu.c193 #define _BUILD_REGION_CONF(reg, _ATTR) \ argument
194 (struct arm_mpu_region) { .name = (reg).dt_name, \
195 .base = (reg).dt_addr, \
196 .limit = (reg).dt_addr + (reg).dt_size, \
/arch/arm/core/cortex_m/
A Dfault.c29 #define STORE_xFAR(reg_var, reg) uint32_t reg_var = (uint32_t)reg argument
32 #define STORE_xFAR(reg_var, reg) argument
/arch/rx/core/
A Dvects.c28 #define SET_OFS1_HOCO_BITS(reg, freq) \ argument
29 ((reg) & ~(0b11 << 12)) | ((((freq) == 24000000 ? 0b10 \
/arch/arm/
A DKconfig73 This setting can be derived from a DT node reg property or specified directly.
95 This setting can be derived from a DT node reg property or specified directly.
/arch/arc/
A DKconfig136 - LP_COUNT core reg
289 Depending on the configuration, CPU can contain accumulator reg-pair

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