| /arch/arm/core/cortex_m/ |
| A D | cache.c | 49 int arch_dcache_flush_range(void *start_addr, size_t size) in arch_dcache_flush_range() argument 51 SCB_CleanDCache_by_Addr(start_addr, size); in arch_dcache_flush_range() 56 int arch_dcache_invd_range(void *start_addr, size_t size) in arch_dcache_invd_range() argument 58 SCB_InvalidateDCache_by_Addr(start_addr, size); in arch_dcache_invd_range() 63 int arch_dcache_flush_and_invd_range(void *start_addr, size_t size) in arch_dcache_flush_and_invd_range() argument 65 SCB_CleanInvalidateDCache_by_Addr(start_addr, size); in arch_dcache_flush_and_invd_range() 97 int arch_icache_flush_range(void *start_addr, size_t size) in arch_icache_flush_range() argument 99 ARG_UNUSED(start_addr); in arch_icache_flush_range() 105 int arch_icache_invd_range(void *start_addr, size_t size) in arch_icache_invd_range() argument 107 SCB_InvalidateICache_by_Addr(start_addr, size); in arch_icache_invd_range() [all …]
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| /arch/arc/core/ |
| A D | cache.c | 368 end_addr = start_addr + size; in dcache_flush_lines() 370 start_addr = ROUND_DOWN(start_addr, line_size); in dcache_flush_lines() 386 start_addr += line_size; in dcache_flush_lines() 387 } while (start_addr < end_addr); in dcache_flush_lines() 400 end_addr = start_addr + size; in dcache_invalidate_lines() 401 start_addr = ROUND_DOWN(start_addr, line_size); in dcache_invalidate_lines() 414 start_addr += line_size; in dcache_invalidate_lines() 415 } while (start_addr < end_addr); in dcache_invalidate_lines() 427 end_addr = start_addr + size; in dcache_flush_and_invalidate_lines() 428 start_addr = ROUND_DOWN(start_addr, line_size); in dcache_flush_and_invalidate_lines() [all …]
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| /arch/arm/core/cortex_a_r/ |
| A D | cache.c | 96 int arch_dcache_flush_range(void *start_addr, size_t size) in arch_dcache_flush_range() argument 99 uintptr_t addr = (uintptr_t)start_addr; in arch_dcache_flush_range() 114 int arch_dcache_invd_range(void *start_addr, size_t size) in arch_dcache_invd_range() argument 117 uintptr_t addr = (uintptr_t)start_addr; in arch_dcache_invd_range() 152 int arch_dcache_flush_and_invd_range(void *start_addr, size_t size) in arch_dcache_flush_and_invd_range() argument 155 uintptr_t addr = (uintptr_t)start_addr; in arch_dcache_flush_and_invd_range() 204 int arch_icache_flush_range(void *start_addr, size_t size) in arch_icache_flush_range() argument 206 ARG_UNUSED(start_addr); in arch_icache_flush_range() 212 int arch_icache_invd_range(void *start_addr, size_t size) in arch_icache_invd_range() argument 214 ARG_UNUSED(start_addr); in arch_icache_invd_range() [all …]
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| /arch/x86/core/ |
| A D | cache.c | 88 int arch_dcache_flush_range(void *start_addr, size_t size) in arch_dcache_flush_range() argument 91 uintptr_t start = (uintptr_t)start_addr; in arch_dcache_flush_range() 113 int arch_dcache_invd_range(void *start_addr, size_t size) in arch_dcache_invd_range() argument 115 return arch_dcache_flush_range(start_addr, size); in arch_dcache_invd_range() 118 int arch_dcache_flush_and_invd_range(void *start_addr, size_t size) in arch_dcache_flush_and_invd_range() argument 120 return arch_dcache_flush_range(start_addr, size); in arch_dcache_flush_and_invd_range()
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| /arch/x86/core/ia32/ |
| A D | coredump.c | 89 uintptr_t start_addr, end_addr; in arch_coredump_priv_stack_dump() local 97 start_addr = (uintptr_t)&hdr_stack_obj->privilege_stack[0]; in arch_coredump_priv_stack_dump() 98 end_addr = start_addr + sizeof(hdr_stack_obj->privilege_stack); in arch_coredump_priv_stack_dump() 100 coredump_memory_dump(start_addr, end_addr); in arch_coredump_priv_stack_dump()
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| /arch/riscv/core/ |
| A D | coredump.c | 124 uintptr_t start_addr, end_addr; in arch_coredump_priv_stack_dump() local 128 start_addr = thread->arch.priv_stack_start + Z_RISCV_STACK_GUARD_SIZE; in arch_coredump_priv_stack_dump() 130 start_addr = thread->stack_info.start - CONFIG_PRIVILEGED_STACK_SIZE; in arch_coredump_priv_stack_dump() 135 coredump_memory_dump(start_addr, end_addr); in arch_coredump_priv_stack_dump()
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| /arch/x86/core/intel64/ |
| A D | coredump.c | 115 uintptr_t start_addr, end_addr; in arch_coredump_priv_stack_dump() local 123 start_addr = (uintptr_t)&hdr_stack_obj->privilege_stack[0]; in arch_coredump_priv_stack_dump() 124 end_addr = start_addr + sizeof(hdr_stack_obj->privilege_stack); in arch_coredump_priv_stack_dump() 126 coredump_memory_dump(start_addr, end_addr); in arch_coredump_priv_stack_dump()
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| /arch/xtensa/core/ |
| A D | coredump.c | 198 uintptr_t start_addr, end_addr; in arch_coredump_priv_stack_dump() local 202 start_addr = (uintptr_t)&hdr_stack_obj->privilege_stack[0]; in arch_coredump_priv_stack_dump() 203 end_addr = start_addr + sizeof(hdr_stack_obj->privilege_stack); in arch_coredump_priv_stack_dump() 205 coredump_memory_dump(start_addr, end_addr); in arch_coredump_priv_stack_dump()
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| A D | mpu.c | 410 uintptr_t start_addr, uintptr_t end_addr, in mpu_map_region_add() argument 421 if (start_addr >= end_addr) { in mpu_map_region_add() 447 xtensa_mpu_entry_set(entry_slot_s, start_addr, true, in mpu_map_region_add() 462 xtensa_mpu_entry_set(entry_slot_s, start_addr, true, in mpu_map_region_add() 484 check_addr_in_mpu_entries(entries, start_addr, first_enabled_idx, in mpu_map_region_add() 492 __ASSERT_NO_MSG(start_addr < end_addr); in mpu_map_region_add() 539 xtensa_mpu_entry_set(entry_slot_s, start_addr, true, access_rights, memory_type); in mpu_map_region_add() 574 check_addr_in_mpu_entries(entries, start_addr, first_enabled_idx, in mpu_map_region_add()
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| /arch/xtensa/include/ |
| A D | xtensa_mpu_priv.h | 118 .as.p.start_addr = (saddr >> XTENSA_MPU_ENTRY_START_ADDR_SHIFT), \ 201 return (entry->as.p.start_addr << XTENSA_MPU_ENTRY_REG_START_ADDR_SHIFT); in xtensa_mpu_entry_start_address_get() 213 entry->as.p.start_addr = addr >> XTENSA_MPU_ENTRY_REG_START_ADDR_SHIFT; in xtensa_mpu_entry_start_address_set()
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