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Searched refs:val (Results 1 – 19 of 19) sorted by relevance

/arch/xtensa/core/
A Dgdbstub.c95 [val] "r" (regval), \
108 uint32_t val; in read_sreg() local
130 val = get_one_sreg(SAR); in read_sreg()
133 val = get_one_sreg(PS); in read_sreg()
154 val = get_one_sreg(DEPC); in read_sreg()
167 val = get_one_sreg(LBEG); in read_sreg()
170 val = get_one_sreg(LEND); in read_sreg()
192 val = 0; in read_sreg()
195 val = 1; in read_sreg()
333 reg->val = val; in read_sreg()
[all …]
A Dgen_vectors.py69 (sym, val) = (m.group(1), m.group(2))
72 assert eval(val) == 0
82 m = re.match(r"XCHAL_INTLEVEL(\d+)_VECOFS", val)
88 if val == "XCHAL_NMI_VECOFS":
93 addr = eval(val)
A Dgen_zsr.py74 for sym, val in syms.items():
75 if val == "XTHAL_INTTYPE_SOFTWARE":
A Dvector_handlers.c221 static inline unsigned int get_bits(int offset, int num_bits, unsigned int val) in get_bits() argument
226 val = val >> offset; in get_bits()
227 return val & mask; in get_bits()
/arch/mips/include/mips/
A Dmipsregs.h35 uint32_t val; \
37 : "=r" (val)); \
38 val; \
41 #define _mips_write_32bit_c0_register(reg, val) \ argument
45 : "Jr" ((uint32_t)(val))); \
49 #define write_c0_status(val) _mips_write_32bit_c0_register(CP0_STATUS, val) argument
/arch/arm/core/cortex_a_r/
A Dcache.c36 uint32_t val; in arch_dcache_line_size_get() local
40 val = read_sysreg(ctr); in arch_dcache_line_size_get()
41 dminline = (val >> CTR_DMINLINE_SHIFT) & CTR_DMINLINE_MASK; in arch_dcache_line_size_get()
51 uint32_t val; in arch_dcache_enable() local
55 val = __get_SCTLR(); in arch_dcache_enable()
56 val |= SCTLR_C_Msk; in arch_dcache_enable()
58 __set_SCTLR(val); in arch_dcache_enable()
64 uint32_t val; in arch_dcache_disable() local
68 val = __get_SCTLR(); in arch_dcache_disable()
69 val &= ~SCTLR_C_Msk; in arch_dcache_disable()
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/arch/x86/core/
A Dearly_serial.c21 #define OUT(reg, val) sys_out8(val, reg + DT_REG_ADDR(DT_CHOSEN(zephyr_console))) argument
29 #define OUT(reg, val) sys_write32((val) & 0xff, mmio + (reg) * 4) argument
41 #define OUT(reg, val) sys_write8(val, BASE + reg) argument
A Dx86_mmu.c367 static inline void pentry_get(int *paging_level, pentry_t *val, in pentry_get() argument
376 *val = entry; in pentry_get()
765 void z_x86_pentry_get(int *paging_level, pentry_t *val, pentry_t *ptables, in z_x86_pentry_get() argument
768 pentry_get(paging_level, val, ptables, virt); in z_x86_pentry_get()
824 static inline pentry_t pte_finalize_value(pentry_t val, bool user_table, in pte_finalize_value() argument
831 if (user_table && (val & MMU_US) == 0 && (val & MMU_P) != 0 && in pte_finalize_value()
832 get_entry_phys(val, level) != shared_phys_addr) { in pte_finalize_value()
833 val = ~val; in pte_finalize_value()
839 return val; in pte_finalize_value()
/arch/arc/core/secureshield/
A Dsecure_sys_services.c39 static int32_t arc_s_aux_write(uint32_t aux_reg, uint32_t val) in arc_s_aux_write() argument
45 val &= IRQ_PRIO_MASK; in arc_s_aux_write()
46 z_arc_v2_aux_reg_write(_ARC_V2_AUX_IRQ_ACT, val | in arc_s_aux_write()
/arch/arm64/core/cortex_r/
A Darm_mpu.c96 uint64_t val; in arm_core_mpu_enable() local
98 val = read_sctlr_el1(); in arm_core_mpu_enable()
99 val |= SCTLR_M_BIT; in arm_core_mpu_enable()
100 write_sctlr_el1(val); in arm_core_mpu_enable()
110 uint64_t val; in arm_core_mpu_disable() local
116 val &= ~SCTLR_M_BIT; in arm_core_mpu_disable()
117 write_sctlr_el1(val); in arm_core_mpu_disable()
263 uint64_t val; in z_arm64_mm_init() local
351 uint64_t val; in arm_core_mpu_background_region_enable() local
354 val |= SCTLR_BR_BIT; in arm_core_mpu_background_region_enable()
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/arch/arc/core/
A Dcache.c66 val &= 0xff; /* extract version */ in dcache_available()
67 return (val == 0) ? false : true; in dcache_available()
87 uint32_t val = z_arc_v2_aux_reg_read(_ARC_V2_SLC_CTRL); in slc_enable() local
89 val &= ~SLC_CTRL_DISABLE; in slc_enable()
90 z_arc_v2_aux_reg_write(_ARC_V2_SLC_CTRL, val); in slc_enable()
598 uint32_t val; in init_dcache_line_size() local
600 val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD); in init_dcache_line_size()
601 __ASSERT((val&0xff) != 0U, "d-cache is not present"); in init_dcache_line_size()
602 val = ((val>>16) & 0xf) + 1; in init_dcache_line_size()
603 val *= 16U; in init_dcache_line_size()
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A Dsmp.c101 bcr.val = z_arc_v2_aux_reg_read(_ARC_V2_CONNECT_BCR); in arch_secondary_cpu_init()
168 bcr.val = z_arc_v2_aux_reg_read(_ARC_V2_CONNECT_BCR); in arch_smp_init()
/arch/arm/core/mpu/
A Darm_mpu.c247 uint32_t val; in arm_core_mpu_enable() local
249 val = __get_SCTLR(); in arm_core_mpu_enable()
250 val |= SCTLR_MPU_ENABLE; in arm_core_mpu_enable()
251 __set_SCTLR(val); in arm_core_mpu_enable()
263 uint32_t val; in arm_core_mpu_disable() local
268 val = __get_SCTLR(); in arm_core_mpu_disable()
269 val &= ~SCTLR_MPU_ENABLE; in arm_core_mpu_disable()
270 __set_SCTLR(val); in arm_core_mpu_disable()
/arch/arc/core/mpu/
A Darc_mpu_v6_internal.h67 uint32_t val; in _bank_select() local
69 val = z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) & (~AUX_MPU_EN_BANK_MASK); in _bank_select()
70 z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, val | bank); in _bank_select()
A Darc_mpu_common_internal.h98 uint32_t val = z_arc_v2_aux_reg_read(_ARC_V2_MPU_EN) & (~AUX_MPU_RDP_ATTR_MASK); in arc_core_mpu_default() local
101 z_arc_v2_aux_reg_write(_ARC_V2_MPU_EN, region_attr | val); in arc_core_mpu_default()
A Darc_mpu_v4_internal.h203 uint32_t val; in _mpu_probe() local
206 val = z_arc_v2_aux_reg_read(_ARC_V2_MPU_INDEX); in _mpu_probe()
209 if (val & 0xC0000000) { in _mpu_probe()
212 return val; in _mpu_probe()
/arch/x86/include/
A Dx86_mmu.h92 void z_x86_pentry_get(int *paging_level, pentry_t *val, pentry_t *ptables,
/arch/x86/
A Dgen_mmu.py169 def round_up(val, align): argument
171 return (val + (align - 1)) & (~(align - 1))
174 def round_down(val, align): argument
176 return val & (~(align - 1))
/arch/arm64/core/
A Dmmu.c964 uint64_t val; in enable_mmu_el1() local
975 val = read_sctlr_el1(); in enable_mmu_el1()
976 write_sctlr_el1(val | SCTLR_M_BIT | SCTLR_C_BIT); in enable_mmu_el1()

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