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/arch/xtensa/core/
A Dgen_zsr.py88 f.write("/* Generated File, see gen_zsr.py */\n")
89 f.write("#ifndef ZEPHYR_ZSR_H\n")
90 f.write("#define ZEPHYR_ZSR_H\n")
92 f.write(f"# define ZSR_{need} {regs[i]}\n")
93 f.write(f"# define ZSR_{need}_STR \"{regs[i]}\"\n")
97 f.write(f"# define ZSR_EXTRA{i - len(NEEDED)} {regs[i]}\n")
101 f.write(f"# define ZSR_RFI_LEVEL {maxint}\n")
102 f.write(f"# define ZSR_EPC EPC{maxint}\n")
103 f.write(f"# define ZSR_EPS EPS{maxint}\n")
107 f.write(f"# define ZSR_IRQ_OFFLOAD_INT {irqoff_int}\n")
[all …]
A Dptables.c1054 static bool page_validate(uint32_t *ptables, uint32_t page, uint8_t ring, bool write) in page_validate() argument
1085 if (write) { in page_validate()
1092 static int mem_buffer_validate(const void *addr, size_t size, int write, int ring) in mem_buffer_validate() argument
1106 if (!page_validate(ptables, (uint32_t)(virt + offset), ring, write)) { in mem_buffer_validate()
1115 bool xtensa_mem_kernel_has_access(const void *addr, size_t size, int write) in xtensa_mem_kernel_has_access() argument
1117 return mem_buffer_validate(addr, size, write, XTENSA_MMU_KERNEL_RING) == 0; in xtensa_mem_kernel_has_access()
1120 int arch_buffer_validate(const void *addr, size_t size, int write) in arch_buffer_validate() argument
1122 return mem_buffer_validate(addr, size, write, XTENSA_MMU_USER_RING); in arch_buffer_validate()
A Dmpu.c1010 int arch_buffer_validate(const void *addr, size_t size, int write) in arch_buffer_validate() argument
1036 if (write) { in arch_buffer_validate()
1081 bool xtensa_mem_kernel_has_access(const void *addr, size_t size, int write) in xtensa_mem_kernel_has_access() argument
1108 if (write != 0) { in xtensa_mem_kernel_has_access()
/arch/x86/zefi/
A Dzefi.py75 cf.write("/* GENERATED CODE. DO NOT EDIT. */\n\n")
77 cf.write("/* Sizes and offsets specified in 4-byte units.\n")
78 cf.write(" * All addresses 4-byte aligned.\n")
79 cf.write(" */\n")
83 cf.write("static struct data_seg zefi_dsegs[] = {\n")
85 cf.write(" { 0x%x, %d, %d },\n"
87 cf.write("};\n\n")
91 cf.write("static struct zero_seg zefi_zsegs[] = {\n")
93 cf.write(" { 0x%x, %d },\n"
95 cf.write("};\n\n")
[all …]
/arch/x86/
A Dgen_gdt.py57 sys.stdout.write(os.path.basename(sys.argv[0]) + ": " + text + "\n")
205 output_fp.write(create_gdt_pseudo_desc(gdt_base, num_entries * 8))
208 output_fp.write(create_code_data_entry(0, 0xFFFFF, 0,
212 output_fp.write(create_code_data_entry(0, 0xFFFFF, 0,
220 output_fp.write(create_tss_entry(main_tss, 0x67, 0))
223 output_fp.write(create_tss_entry(df_tss, 0x67, 0))
227 output_fp.write(create_code_data_entry(0, 0xFFFFF, 3,
231 output_fp.write(create_code_data_entry(0, 0xFFFFF, 3,
240 output_fp.write(create_code_data_entry(0, 0xFFFFF, 3,
A Dgen_idt.py53 sys.stdout.write(os.path.basename(sys.argv[0]) + ": " + text + "\n")
100 fp.write(data)
109 fp.write(struct.pack(map_fmt, i))
288 fp.write(struct.pack("<B", char))
A Dgen_mmu.py119 sys.stdout.write(os.path.basename(sys.argv[0]) + ": " + text + "\n")
125 sys.stdout.write(os.path.basename(sys.argv[0]) + ": " + text + "\n")
566 output_fp.write(mmu_table_bin)
577 output_fp.write(top_level_bin)
/arch/arc/core/mpu/
A Darc_core_mpu.c37 int arch_buffer_validate(const void *addr, size_t size, int write) in arch_buffer_validate() argument
39 return arc_core_mpu_buffer_validate(addr, size, write); in arch_buffer_validate()
A Darc_mpu_v2_internal.h146 static inline bool _is_user_accessible_region(uint32_t r_index, int write) in _is_user_accessible_region() argument
154 if (write) { in _is_user_accessible_region()
A Darc_mpu_v6_internal.h185 static inline bool _is_user_accessible_region(uint32_t r_index, int write) in _is_user_accessible_region() argument
196 if (write) { in _is_user_accessible_region()
A Darc_mpu_common_internal.h210 int arc_core_mpu_buffer_validate(const void *addr, size_t size, int write) in arc_core_mpu_buffer_validate() argument
223 if (_is_user_accessible_region(r_index, write)) { in arc_core_mpu_buffer_validate()
A Darc_mpu_v4_internal.h130 static inline bool _is_user_accessible_region(uint32_t r_index, int write) in _is_user_accessible_region() argument
229 static inline bool _is_user_accessible_region(uint32_t r_index, int write) in _is_user_accessible_region() argument
237 if (write) { in _is_user_accessible_region()
782 int arc_core_mpu_buffer_validate(const void *addr, size_t size, int write) in arc_core_mpu_buffer_validate() argument
795 if (_is_user_accessible_region(r_index, write)) { in arc_core_mpu_buffer_validate()
/arch/arm/core/mpu/
A Darm_mpu_v7_internal.h156 static inline int is_user_accessible_region(uint32_t r_index, int write) in is_user_accessible_region() argument
161 if (write != 0) { in is_user_accessible_region()
172 static inline int mpu_buffer_validate(const void *addr, size_t size, int write) in mpu_buffer_validate() argument
191 if (is_user_accessible_region(r_index, write)) { in mpu_buffer_validate()
A Darm_mpu_v8_internal.h405 static inline int is_user_accessible_region(uint32_t rnr, int write) in is_user_accessible_region() argument
413 if (write != 0) { in is_user_accessible_region()
424 static inline int mpu_buffer_validate(const void *addr, size_t size, int write) in mpu_buffer_validate() argument
438 if (is_user_accessible_region(rnr, write)) { in mpu_buffer_validate()
471 static inline int mpu_buffer_validate(const void *addr, size_t size, int write) in mpu_buffer_validate() argument
476 if (write) { in mpu_buffer_validate()
496 if (write) { in mpu_buffer_validate()
A Darm_core_mpu_dev.h264 int arm_core_mpu_buffer_validate(const void *addr, size_t size, int write);
A Dnxp_mpu.c591 static inline int is_user_accessible_region(uint32_t r_index, int write) in is_user_accessible_region() argument
595 if (write != 0) { in is_user_accessible_region()
605 int arm_core_mpu_buffer_validate(const void *addr, size_t size, int write) in arm_core_mpu_buffer_validate() argument
621 if (is_user_accessible_region(r_index, write)) { in arm_core_mpu_buffer_validate()
A Darm_core_mpu.c367 int arch_buffer_validate(const void *addr, size_t size, int write) in arch_buffer_validate() argument
369 return arm_core_mpu_buffer_validate(addr, size, write); in arch_buffer_validate()
A Darm_mpu.c365 int arm_core_mpu_buffer_validate(const void *addr, size_t size, int write) in arm_core_mpu_buffer_validate() argument
367 return mpu_buffer_validate(addr, size, write); in arm_core_mpu_buffer_validate()
A DKconfig44 bool "Add MPU access to write to flash"
/arch/x86/core/
A Dpcie.c66 bool write, uint32_t *data) in pcie_mm_conf() argument
79 if (write) { in pcie_mm_conf()
105 bool write, uint32_t *data) in pcie_io_conf() argument
117 if (write) { in pcie_io_conf()
128 bool write, uint32_t *data) in pcie_conf() argument
137 pcie_mm_conf(bdf, reg, write, data); in pcie_conf()
141 pcie_io_conf(bdf, reg, write, data); in pcie_conf()
A Dx86_mmu.c1395 static bool page_validate(pentry_t *ptables, uint8_t *addr, bool write) in page_validate() argument
1416 (write && ((entry & MMU_RW) == 0U))) { in page_validate()
1442 int arch_buffer_validate(const void *addr, size_t size, int write) in arch_buffer_validate() argument
1455 if (!page_validate(ptables, virt + offset, write)) { in arch_buffer_validate()
/arch/xtensa/include/
A Dxtensa_internal.h75 bool xtensa_mem_kernel_has_access(const void *addr, size_t size, int write);
/arch/arm64/core/cortex_r/
A DKconfig24 bool "Add MPU access to write to flash"
/arch/riscv/core/
A Dpmp.c759 int arch_buffer_validate(const void *addr, size_t size, int write) in arch_buffer_validate() argument
771 if (!write) { in arch_buffer_validate()
802 if ((part->attr.pmp_attr & (write ? PMP_W : PMP_R)) != 0) { in arch_buffer_validate()
/arch/arm64/core/
A Dmmu.c1650 bool write = (GET_ESR_ISS(esr) & BIT(6)) != 0; /* WnR */ in z_arm64_do_demand_paging() local
1656 if (write) { in z_arm64_do_demand_paging()
1678 if (dfsc == (0b001100 | XLAT_LAST_LEVEL) && write && in z_arm64_do_demand_paging()

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