1 /*
2  * Copyright (c) 2025, Ambiq Micro Inc. <www.ambiq.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 enum memc_mspi_aps_z8_rlc {
8 	MEMC_MSPI_APS_Z8_RLC_4,
9 	MEMC_MSPI_APS_Z8_RLC_5,
10 	MEMC_MSPI_APS_Z8_RLC_6,
11 	MEMC_MSPI_APS_Z8_RLC_7,
12 	MEMC_MSPI_APS_Z8_RLC_8,
13 	MEMC_MSPI_APS_Z8_RLC_9,
14 };
15 
16 enum memc_mspi_aps_z8_wlc {
17 	MEMC_MSPI_APS_Z8_WLC_3, /* reserved for APS51216BA */
18 	MEMC_MSPI_APS_Z8_WLC_7,
19 	MEMC_MSPI_APS_Z8_WLC_5,
20 	MEMC_MSPI_APS_Z8_WLC_9, /* reserved for APS25616N */
21 	MEMC_MSPI_APS_Z8_WLC_4, /* reserved for APS51216BA */
22 	MEMC_MSPI_APS_Z8_WLC_8, /* reserved for APS25616N */
23 	MEMC_MSPI_APS_Z8_WLC_6,
24 	MEMC_MSPI_APS_Z8_WLC_10, /* reserved for APS25616N */
25 };
26 
27 /* default for APS51216BA */
28 #define MEMC_MSPI_APS_Z8_RX_DUMMY_DEFAULT 6
29 #define MEMC_MSPI_APS_Z8_TX_DUMMY_DEFAULT 6
30 
31 #define MEMC_MSPI_APS_Z8_CMD_LENGTH_DEFAULT  1
32 #define MEMC_MSPI_APS_Z8_ADDR_LENGTH_DEFAULT 4
33 
34 enum memc_mspi_aps_z8_ds {
35 	MEMC_MSPI_APS_Z8_DRIVE_STRENGTH_FULL,
36 	MEMC_MSPI_APS_Z8_DRIVE_STRENGTH_HALF,
37 	MEMC_MSPI_APS_Z8_DRIVE_STRENGTH_QUARTER,
38 	MEMC_MSPI_APS_Z8_DRIVE_STRENGTH_OCTUPLE,
39 };
40 
41 struct memc_mspi_aps_z8_reg {
42 	union {
43 		uint8_t MR0;                    /* Mode register 0                      */
44 
45 		struct {
46 			uint8_t DS:         2;  /* [0..1] drive strength                */
47 			uint8_t RLC:        3;  /* [2..4] Read latency code.            */
48 			uint8_t LT:         1;  /* [5..5] Latency type                  */
49 			uint8_t:            1;
50 			uint8_t TSO:        1;  /* [7..7] Temperature Sensor Override   */
51 		} MR0_b;
52 	};
53 
54 	union {
55 		uint8_t MR1;                    /* Mode register 1                      */
56 
57 		struct {
58 			uint8_t VID:        5;  /* [0..4] Vendor ID                     */
59 			uint8_t:            2;
60 			uint8_t ULP:        1;  /* [7..7] Half sleep.                   */
61 		} MR1_b;
62 	};
63 
64 	union {
65 		uint8_t MR2;                    /* Mode register 2                      */
66 
67 		struct {
68 			uint8_t DENSITY:    3;  /* [0..2] Density                       */
69 			uint8_t GENERATION: 2;  /* [3..4] Generation                    */
70 			uint8_t GB:         3;  /* [5..7] Good or bad                   */
71 		} MR2_b;
72 	};
73 
74 	union {
75 		uint8_t MR3;                    /* Mode register 3                      */
76 
77 		struct {
78 			uint8_t:            4;
79 			uint8_t SRF:        2;  /* [4..5] Self refresh flag             */
80 			uint8_t:            1;
81 			uint8_t RBXen:      1;  /* [7..7] Row Boundary Crossing Enable  */
82 		} MR3_b;
83 	};
84 
85 	union {
86 		uint8_t MR4;                    /* Mode register 4                      */
87 
88 		struct {
89 			uint8_t PASR:       3;  /* [0..2] control refresh address space */
90 			uint8_t RFS:        2;  /* [3..4] Refresh Frequency setting     */
91 			uint8_t WLC:        3;  /* [5..7] Write latency code.           */
92 		} MR4_b;
93 	};
94 
95 	union {
96 		uint8_t MR6;                    /* Mode register 6                      */
97 
98 		struct {
99 			uint8_t ULPM:       8;  /* [0..7] ULP modes                     */
100 		} MR6_b;
101 	};
102 
103 	union {
104 		uint8_t MR8;                    /* Mode register 8                      */
105 
106 		struct {
107 			uint8_t BL:         2;  /* [0..1] Burst Length                  */
108 			uint8_t BT:         1;  /* [2..2] Burst type                    */
109 			uint8_t RBX:        1;  /* [3..3] Row Boundary Crossing Read EN */
110 			uint8_t:            2;
111 			uint8_t IOM:        1;  /* [6..6] IO mode                       */
112 			uint8_t:            1;
113 		} MR8_b;
114 	};
115 };
116