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Searched refs:CR (Results 1 – 25 of 32) sorted by relevance

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/drivers/flash/
A Dflash_stm32u3x.c56 if (regs->CR & FLASH_STM32_NSLOCK) { in write_nwords()
90 regs->CR |= FLASH_STM32_NSPG; in write_nwords()
93 tmp = regs->CR; in write_nwords()
104 regs->CR &= ~FLASH_STM32_NSPG; in write_nwords()
146 regs->CR |= FLASH_STM32_NSBKER; in erase_page()
151 regs->CR |= FLASH_STM32_NSBKER; in erase_page()
164 regs->CR |= FLASH_STM32_NSPER; in erase_page()
165 regs->CR &= ~FLASH_STM32_NSPNB_MSK; in erase_page()
169 regs->CR |= FLASH_STM32_NSSTRT; in erase_page()
172 tmp = regs->CR; in erase_page()
[all …]
A Dflash_stm32l4x.c81 if (regs->CR & FLASH_CR_LOCK) { in write_dword()
114 regs->CR |= FLASH_CR_PG; in write_dword()
117 tmp = regs->CR; in write_dword()
127 regs->CR &= (~FLASH_CR_PG); in write_dword()
191 regs->CR |= FLASH_CR_PER; in erase_page()
196 regs->CR |= FLASH_CR_BKER; in erase_page()
199 regs->CR &= ~FLASH_CR_PNB_Msk; in erase_page()
203 regs->CR |= FLASH_CR_STRT; in erase_page()
206 tmp = regs->CR; in erase_page()
211 regs->CR &= ~FLASH_CR_PER; in erase_page()
[all …]
A Dflash_stm32f2x.c62 if (regs->CR & FLASH_CR_LOCK) { in write_byte()
72 regs->CR &= ~FLASH_CR_PSIZE; in write_byte()
73 regs->CR |= FLASH_PSIZE_BYTE; in write_byte()
74 regs->CR |= FLASH_CR_PG; in write_byte()
77 tmp = regs->CR; in write_byte()
85 regs->CR &= (~FLASH_CR_PG); in write_byte()
97 if (regs->CR & FLASH_CR_LOCK) { in erase_sector()
107 regs->CR &= ~FLASH_CR_SNB; in erase_sector()
108 regs->CR |= FLASH_CR_SER | (sector << 3); in erase_sector()
109 regs->CR |= FLASH_CR_STRT; in erase_sector()
[all …]
A Dflash_stm32g4x.c87 if (regs->CR & FLASH_CR_LOCK) { in write_dword()
121 regs->CR |= FLASH_CR_PG; in write_dword()
124 tmp = regs->CR; in write_dword()
134 regs->CR &= (~FLASH_CR_PG); in write_dword()
184 regs->CR |= FLASH_CR_BKER; in erase_page()
189 regs->CR |= FLASH_CR_BKER; in erase_page()
202 regs->CR |= FLASH_CR_PER; in erase_page()
207 regs->CR |= FLASH_CR_STRT; in erase_page()
210 tmp = regs->CR; in erase_page()
220 regs->CR &= ~(FLASH_CR_PER); in erase_page()
[all …]
A Dflash_stm32wbx.c72 if (regs->CR & FLASH_CR_LOCK) { in write_dword()
160 regs->CR |= FLASH_CR_PG; in write_dword()
163 tmp = regs->CR; in write_dword()
197 regs->CR &= (~FLASH_CR_PG); in write_dword()
212 if (regs->CR & FLASH_CR_LOCK) { in erase_page()
296 regs->CR |= FLASH_CR_PER; in erase_page()
297 regs->CR &= ~FLASH_CR_PNB_Msk; in erase_page()
298 regs->CR |= page << FLASH_CR_PNB_Pos; in erase_page()
300 regs->CR |= FLASH_CR_STRT; in erase_page()
328 regs->CR &= ~FLASH_CR_PER; in erase_page()
A Dflash_stm32f4x.c93 if (regs->CR & FLASH_CR_LOCK) { in write_value()
113 regs->CR &= CR_PSIZE_MASK; in write_value()
114 regs->CR |= FLASH_PROGRAM_SIZE; in write_value()
115 regs->CR |= FLASH_CR_PG; in write_value()
118 tmp = regs->CR; in write_value()
123 regs->CR &= (~FLASH_CR_PG); in write_value()
144 if (regs->CR & FLASH_CR_LOCK) { in erase_sector()
171 regs->CR &= CR_PSIZE_MASK; in erase_sector()
174 regs->CR &= ~FLASH_CR_SNB; in erase_sector()
176 regs->CR |= FLASH_CR_STRT; in erase_sector()
[all …]
A Dflash_stm32g0x.c65 if (regs->CR & FLASH_CR_LOCK) { in write_dword()
87 regs->CR |= FLASH_CR_PG; in write_dword()
90 tmp = regs->CR; in write_dword()
100 regs->CR &= (~FLASH_CR_PG); in write_dword()
113 if (regs->CR & FLASH_CR_LOCK) { in erase_page()
130 tmp = regs->CR; in erase_page()
155 regs->CR = tmp; in erase_page()
160 regs->CR &= ~FLASH_CR_PER; in erase_page()
A Dflash_stm32f7x.c47 if (regs->CR & FLASH_CR_LOCK) { in write_byte()
57 regs->CR = (regs->CR & CR_PSIZE_MASK) | in write_byte()
68 regs->CR &= (~FLASH_CR_PG); in write_byte()
79 if (regs->CR & FLASH_CR_LOCK) { in erase_sector()
103 regs->CR = (regs->CR & ~(FLASH_CR_PSIZE | FLASH_CR_SNB)) | in erase_sector()
112 regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB); in erase_sector()
A Dflash_stm32f1x.c50 return !!(regs->CR & FLASH_CR_LOCK); in is_flash_locked()
55 regs->CR |= FLASH_CR_PG; in write_enable()
60 regs->CR &= (~FLASH_CR_PG); in write_disable()
66 regs->CR |= FLASH_CR_PER; in erase_page_begin()
72 regs->CR |= FLASH_CR_STRT; in erase_page_begin()
77 regs->CR &= ~FLASH_CR_PER; in erase_page_end()
A Dflash_stm32_ex_op.c47 regs->CR &= ~FLASH_CR_OPTWRE; in flash_stm32_option_bytes_lock()
48 } else if (!(regs->CR & FLASH_CR_OPTWRE)) { in flash_stm32_option_bytes_lock()
54 regs->CR |= FLASH_CR_OPTLOCK; in flash_stm32_option_bytes_lock()
55 } else if (regs->CR & FLASH_CR_OPTLOCK) { in flash_stm32_option_bytes_lock()
A Dflash_stm32.c266 regs->CR |= FLASH_CR_LOCK; in flash_stm32_cr_lock()
268 if (regs->CR & FLASH_CR_LOCK) { in flash_stm32_cr_lock()
314 regs->CR |= FLASH_CR_LOCK; in flash_stm32_control_register_disable()
A Dflash_stm32.h52 #define CR1 CR
/drivers/spi/spi_nxp_lpspi/
A Dspi_nxp_lpspi_common.c260 base->CR |= LPSPI_CR_DBGEN_MASK; in lpspi_basic_config()
298 base->CR |= LPSPI_CR_RST_MASK; in lpspi_configure()
299 base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; in lpspi_configure()
302 base->CR = 0; in lpspi_configure()
303 while ((base->CR & LPSPI_CR_MEN_MASK) != 0) { in lpspi_configure()
326 base->CR |= LPSPI_CR_MEN_MASK; in lpspi_configure()
382 base->CR |= LPSPI_CR_RST_MASK; in spi_nxp_init_common()
383 base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; in spi_nxp_init_common()
384 base->CR = 0x00U; in spi_nxp_init_common()
A Dspi_nxp_lpspi.c213 base->CR |= LPSPI_CR_RTF_MASK; in lpspi_handle_tx_irq()
265 base->CR |= LPSPI_CR_RRF_MASK; /* flush rx fifo */ in lpspi_isr()
391 base->CR |= LPSPI_CR_RRF_MASK; in transceive()
420 base->CR |= LPSPI_CR_MEN_MASK; in transceive()
/drivers/input/
A Dinput_tsc_keys.c98 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_START_Pos); in stm32_tsc_start()
204 sys_set_bits((mem_addr_t)&config->tsc->CR, (((config->ctph - 1) << 4) | (config->ctpl - 1)) in stm32_tsc_init()
208 sys_set_bits((mem_addr_t)&config->tsc->CR, config->ssd << TSC_CR_SSD_Pos); in stm32_tsc_init()
211 sys_set_bits((mem_addr_t)&config->tsc->CR, config->pgpsc << TSC_CR_PGPSC_Pos); in stm32_tsc_init()
214 sys_set_bits((mem_addr_t)&config->tsc->CR, config->max_count << TSC_CR_MCV_Pos); in stm32_tsc_init()
218 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SSPSC_Pos); in stm32_tsc_init()
223 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SYNCPOL_Pos); in stm32_tsc_init()
228 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_AM_Pos); in stm32_tsc_init()
233 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_IODEF_Pos); in stm32_tsc_init()
238 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SSE_Pos); in stm32_tsc_init()
[all …]
/drivers/usb_c/tcpc/
A Ducpd_stm32.c278 cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in ucpd_set_vconn()
283 LL_UCPD_WriteReg(config->ucpd_port, CR, cr); in ucpd_set_vconn()
374 cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in dead_battery()
382 LL_UCPD_WriteReg(config->ucpd_port, CR, cr); in dead_battery()
412 cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in ucpd_set_cc()
434 LL_UCPD_WriteReg(config->ucpd_port, CR, cr); in ucpd_set_cc()
457 cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in ucpd_cc_set_polarity()
475 LL_UCPD_WriteReg(config->ucpd_port, CR, cr); in ucpd_cc_set_polarity()
493 cr = LL_UCPD_ReadReg(config->ucpd_port, CR); in ucpd_set_rx_enable()
505 LL_UCPD_WriteReg(config->ucpd_port, CR, cr); in ucpd_set_rx_enable()
[all …]
/drivers/serial/
A Duart_pl011_ambiq.h124 UARTn(ui32Module)->CR = pRegisterStatus->regCR; in uart_ambiq_pm_action()
144 pRegisterStatus->regCR = UARTn(ui32Module)->CR; in uart_ambiq_pm_action()
162 UARTn(ui32Module)->CR = 0; in uart_ambiq_pm_action()
A Duart_ambiq.c228 if (!(UARTn(config->inst_idx)->CR & UART0_CR_UARTEN_Msk) || in uart_ambiq_is_readable()
229 !(UARTn(config->inst_idx)->CR & UART0_CR_RXE_Msk)) { in uart_ambiq_is_readable()
416 if (!(UARTn(cfg->inst_idx)->CR & UART0_CR_TXE_Msk)) { in uart_ambiq_irq_tx_ready()
449 if (!(UARTn(cfg->inst_idx)->CR & UART0_CR_RXE_Msk)) { in uart_ambiq_irq_rx_ready()
/drivers/i2c/
A Di2c_sam4l_twim.c294 twim->CR = TWIM_CR_MEN; in i2c_start_xfer()
295 twim->CR = TWIM_CR_SWRST; in i2c_start_xfer()
296 twim->CR = TWIM_CR_MDIS; in i2c_start_xfer()
372 twim->CR = TWIM_CR_MEN; in i2c_start_xfer()
567 twim->CR = TWIM_CR_MEN; in i2c_sam_twim_initialize()
570 twim->CR |= TWIM_CR_SWRST; in i2c_sam_twim_initialize()
/drivers/ethernet/
A Deth_smsc91x_priv.h61 #define CR 0x0 macro
/drivers/video/
A Dvideo_stm32_dcmi.c270 data->hdcmi.Instance->CR &= ~(DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1); in video_stm32_dcmi_set_stream()
271 data->hdcmi.Instance->CR |= STM32_DCMI_GET_CAPTURE_RATE(data->capture_rate); in video_stm32_dcmi_set_stream()
/drivers/entropy/
A Dentropy_stm32.c212 cur_nist_cfg = READ_BIT(rng->CR, in configure_rng()
227 MODIFY_REG(rng->CR, cur_nist_cfg, (desired_nist_cfg | RNG_CR_CONDRST)); in configure_rng()
/drivers/mdio/
A Dmdio_nxp_enet_qos.c255 ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, CR, divider); in nxp_enet_qos_mdio_init()
/drivers/pwm/
A Dpwm_mcux_pwt.c228 if (config->base->CR & PWT_CR_LVL_MASK) { in mcux_pwt_isr()
/drivers/memc/
A Dmemc_stm32_xspi_psram.c356 MODIFY_REG(hxspi.Instance->CR, XSPI_CR_NOPREF, HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE); in memc_stm32_xspi_psram_init()

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