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Searched refs:DEV_BASE (Results 1 – 12 of 12) sorted by relevance

/drivers/dma/
A Ddma_mcux_edma.c246 EDMA_GetErrorStatusFlags(DEV_BASE(dev))); in dma_mcux_edma_error_irq_handler()
345 EDMA_TcdSetTransferConfigExt(DEV_BASE(dev), in dma_mcux_edma_configure_sg_loop()
350 EDMA_TcdEnableInterruptsExt(DEV_BASE(dev), in dma_mcux_edma_configure_sg_loop()
618 LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR); in dma_mcux_edma_start()
875 LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR); in dma_mcux_edma_get_status()
876 LOG_DBG("DMA INT 0x%x", DEV_BASE(dev)->INT); in dma_mcux_edma_get_status()
877 LOG_DBG("DMA ERQ 0x%x", DEV_BASE(dev)->ERQ); in dma_mcux_edma_get_status()
878 LOG_DBG("DMA ES 0x%x", DEV_BASE(dev)->ES); in dma_mcux_edma_get_status()
879 LOG_DBG("DMA ERR 0x%x", DEV_BASE(dev)->ERR); in dma_mcux_edma_get_status()
880 LOG_DBG("DMA HRS 0x%x", DEV_BASE(dev)->HRS); in dma_mcux_edma_get_status()
[all …]
A Ddma_mcux_lpc.c76 #define DEV_BASE(dev) \ macro
118 DMA_IRQHandle(DEV_BASE(dev)); in dma_mcux_lpc_irq_handler()
540 DMA_CreateHandle(p_handle, DEV_BASE(dev), channel); in dma_mcux_lpc_configure()
589 DEV_BASE(dev)->CHANNEL[ChannelToDisable].CFG &= in dma_mcux_lpc_configure()
608 DEV_BASE(dev)->CHANNEL[config->linked_channel].CFG |= in dma_mcux_lpc_configure()
632 DEV_BASE(dev)->CHANNEL[ChannelToDisable].CFG &= in dma_mcux_lpc_configure()
809 LOG_DBG("DMA CTRL 0x%x", DEV_BASE(dev)->CTRL); in dma_mcux_lpc_start()
830 DMA_DisableChannel(DEV_BASE(dev), p_handle->channel); in dma_mcux_lpc_stop()
912 LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CTRL); in dma_mcux_lpc_get_status()
913 LOG_DBG("DMA INT 0x%x", DEV_BASE(dev)->INTSTAT); in dma_mcux_lpc_get_status()
[all …]
/drivers/serial/
A Dleuart_gecko.c22 #define DEV_BASE(dev) \ macro
52 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_poll_in()
65 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_poll_out()
75 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_err_check()
103 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_fifo_fill()
118 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_fifo_read()
132 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_irq_tx_enable()
140 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_irq_tx_disable()
148 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_irq_tx_complete()
156 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_irq_tx_ready()
[all …]
A Duart_renesas_rx_sci.c32 #define DEV_BASE(dev) (DEV_CFG(dev)->regs) macro
74 volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); in uart_rx_sci_poll_in()
92 volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); in uart_rx_sci_poll_out()
102 volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); in uart_rx_err_check()
233 volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); in uart_rx_fifo_fill()
246 volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); in uart_rx_fifo_read()
260 volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); in uart_rx_irq_tx_enable()
280 volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); in uart_rx_irq_tx_disable()
288 volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); in uart_rx_irq_tx_ready()
296 volatile struct st_sci *sci = (struct st_sci *)DEV_BASE(dev); in uart_rx_irq_tx_complete()
[all …]
/drivers/i2c/
A Di2c_bcm_iproc.c177 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_enable_disable()
191 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_reset_controller()
210 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_target_set_address()
230 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_target_init()
274 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_check_target_status()
306 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_target_read()
343 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_target_rx()
373 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_target_isr()
461 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_target_register()
485 mem_addr_t base = DEV_BASE(dev); in iproc_i2c_target_unregister()
[all …]
A Di2c_cc32xx.c43 #define DEV_BASE(dev) \ macro
87 uint32_t base = DEV_BASE(dev); in i2c_cc32xx_configure()
119 uint32_t base = DEV_BASE(dev); in i2c_cc32xx_prime_transfer()
265 uint32_t base = DEV_BASE(dev); in i2c_cc32xx_isr()
327 uint32_t base = DEV_BASE(dev); in i2c_cc32xx_init()
A Di2c_imx.c23 #define DEV_BASE(dev) \ macro
53 I2C_Type *base = DEV_BASE(dev); in i2c_imx_write()
87 I2C_Type *base = DEV_BASE(dev); in i2c_imx_read()
127 I2C_Type *base = DEV_BASE(dev); in i2c_imx_configure()
191 I2C_Type *base = DEV_BASE(dev); in i2c_imx_transfer()
273 I2C_Type *base = DEV_BASE(dev); in i2c_imx_isr()
A Di2c_mcux.c25 #define DEV_BASE(dev) \ macro
54 I2C_Type *base = DEV_BASE(dev); in i2c_mcux_configure()
147 I2C_Type *base = DEV_BASE(dev); in i2c_mcux_transfer()
237 I2C_Type *base = DEV_BASE(dev); in i2c_mcux_async_iter()
304 I2C_Type *base = DEV_BASE(dev); in i2c_mcux_isr()
312 I2C_Type *base = DEV_BASE(dev); in i2c_mcux_init()
A Di2c_gecko.c26 #define DEV_BASE(dev) ((I2C_TypeDef *)((const struct i2c_gecko_config *const)(dev)->config)->base) macro
49 I2C_TypeDef *base = DEV_BASE(dev); in i2c_gecko_configure()
91 I2C_TypeDef *base = DEV_BASE(dev); in i2c_gecko_transfer()
A Di2c_lpc11u6x.c15 #define DEV_BASE(dev) (((struct lpc11u6x_i2c_config *)(dev->config))->base) macro
176 struct lpc11u6x_i2c_regs *i2c = DEV_BASE(dev); in lpc11u6x_i2c_isr()
/drivers/clock_control/
A Dclock_control_rv32m1_pcc.c21 #define DEV_BASE(dev) \ macro
29 return MAKE_PCC_REGADDR(DEV_BASE(dev), offset); in clock_ip()
A Dclock_control_mcux_pcc.c27 #define DEV_BASE(dev) (((struct mcux_pcc_config *)(dev->config))->base_address) macro
43 *clock_encoding = MAKE_PCC_REGADDR(DEV_BASE(dev), clock_name); in get_clock_encoding()

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