Searched refs:FIFO (Results 1 – 25 of 30) sorted by relevance
12
15 bool "ITE IT51XXX Shared/Group FIFO Mode Support"19 Enable ITE IT51XXX shared and group FIFO mode. Due to hardware20 limitations, FIFO mode is only supported under the following23 is even and less than SPI_ITE_IT51XXX_FIFO_SIZE (the FIFO size30 int "ITE IT51XXX Shared/Group FIFO Size"35 Set IT51XXX FIFO size. The maximum settable value, as per the
15 FIFO mode for read/write.22 bool "IT51XXX I2C FIFO mode"25 This is an option to enable FIFO mode which can reduce the time30 I2C FIFO mode of IT51XXX can support I2C APIs including:38 int "It is allowed to configure the dedicated FIFO size up to 256 bytes."42 int "It is allowed to configure the shared FIFO size up to 256 bytes."49 This option is used when the I2C target shared FIFO property is enabled.
18 bool "IT8XXX2 I2C FIFO mode"21 This is an option to enable FIFO mode which can reduce26 I2C FIFO mode of it8xxx2 can support I2C APIs including:
64 Double Endpoint Buffer acceleration (DEB) is doubles an EP's FIFO size so66 load/unload data from the EP FIFO. This hex value is a bitmap of endpoints69 FIFO size. Proper calculation should be done before enabling DEB such that70 the total usage of FIFO for all endpoint doesn't exceed the FIFO available71 on SoC. The list of Soc with its FIFO size is listed below. The FIFO size73 - Apollo510: (4096 Bytes FIFO)
27 int "Status FIFO and control FIFO heap"32 storing status FIFO and control FIFO words which will be used by the DMA.
32 hex "ESP32 UART TX FIFO Threshold"37 Configure the TX FIFO threshold for ESP32 UART driver.40 hex "ESP32 UART RX FIFO Threshold"45 Configure the RX FIFO threshold for ESP32 UART driver.
30 Port 0 RX Threshold at which the RX FIFO interrupt triggers.37 Port 0 TX Threshold at which the TX FIFO interrupt triggers.53 Port 1 RX Threshold at which the RX FIFO interrupt triggers.60 Port 1 TX Threshold at which the TX FIFO interrupt triggers.
20 bool "RA SCI_B UART FIFO usage enable"24 Enable RA SCI_B FIFO
21 bool "RA SCI UART FIFO usage enable"24 Enable RA SCI FIFO
48 bool "UART 16550 (16-bytes FIFO)"50 This enables support for 16-bytes FIFO if UART controller is 16550.53 bool "UART 16750 (64-bytes FIFO and auto flow control)"55 This enables support for 64-bytes FIFO and automatic hardware59 bool "UART 16950 (128-bytes FIFO and auto flow control)"61 This enables support for 128-bytes FIFO and automatic hardware flow control.
30 bool "Extended NPCX UART FIFO driver support"33 This option enables the extended UART FIFO driver for NPCKN variant
24 int "Number of CAN messages allocated to each RX FIFO"28 Defines the number of CAN messages in each RX FIFO. A separate RX FIFO
15 bool "NXP S32 CANXL uses RX FIFO"18 If this is enabled, NXP S32 CANXL uses RX FIFO.
32 bool "FIFO rolls on full"34 Controls the behavior of the FIFO when the FIFO becomes completely35 filled with data. If set, the FIFO address rolls over to zero and the36 FIFO continues to fill with new data. If not set, then the FIFO is41 int "FIFO almost full value"
7 bool "FIFO Partitioning"9 FIFO partition feature32 with the DRAIN bit flag set to allow for the hardware FIFO to be drained
55 *data++ = TRNG0->FIFO; in entropy_gecko_trng_read()62 tmp = TRNG0->FIFO; in entropy_gecko_trng_read()
25 int "Size (in bytes) of a FIFO word"29 FIFO word.
22 must be a multiple of TX FIFO block size.39 must be a multiple of RX FIFO block size.83 internal FIFO on to the internal MII/GMII interface, passing through
100 #define FIFO 0x04 macro
25 bool "Use hardware FIFO to stream data"
38 bool "Use hardware FIFO to stream data"
40 bool "Use FIFO to stream data"
58 Enable SDMMC Hardware Flow Control to avoid FIFO underrun (TX mode) and
60 bool "Use hardware FIFO to stream data"
27 bool "Use hardware FIFO to stream data"
Completed in 35 milliseconds